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data sheet, v1.0, apr. 2008 microcontrollers TC1762 32-bit single-chip microcontroller tricore
edition 2008-04 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2008. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in t he human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v1.0, apr. 2008 microcontrollers TC1762 32-bit single-chip microcontroller tricore
TC1762 preliminary data sheet v1.0, 2008-04 trademarks tricore? is a trademark of infineon technologies ag. TC1762 data sheet revision history: v1.0, 2008-04 previous version: v0.5 2007-03 page subjects (major chang es since last revision) 7 vssosc3 is deleted from the TC1762 logic symbol. 8 , 10 tdata0 of pin 17, tclk0 of pin 20, tclk0 of pin 74 and tdata0 of pin 77 are updated in the pinning diagram and pin definition and functions table. 33 transmit dma request in block diagram of asc interfaces is updated. 35 alternate output functions in block di agram of ssc interf aces are updated. 41 programmable baud rate of the mli is updated. 42 tdata0 and tclk0 of the block diagram of mli interfaces are updated. 54 the description for wdt doubl e reset detection is updated. 91 the power sequencing details is updated. 102 mli timing, maximum operat ing frequency limit is extended, t31 is added. 106 thermal resistance junc tion leads is updated. we listen to your comments any information within this docu ment that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
TC1762 table of contents preliminary data sheet 1 v1.0, 2008-04 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4 pad driver and i nput classes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.5 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1 system architecture and on-chip bus systems . . . . . . . . . . . . . . . . . . . . .24 3.2 on-chip memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.3 architectural address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.4 memory protection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.5 dma controller and memory che cker . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.6 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.7 asynchronous/synchronous serial interfac es (asc0, asc1) . . . . . . . . . . .33 3.8 high-speed synchronous serial interface (ssc0) . . . . . . . . . . . . . . . . . . .35 3.9 micro second bus interface (msc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.10 multican controller (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.11 micro link serial bus interfac e (mli0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.12 general purpose timer array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.12.1 functionality of gpta0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.13 analog-to-digital converter (a dc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.14 fast analog-to-digital converter unit (fadc) . . . . . . . . . . . . . . . . . . . . . . .49 3.15 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.16 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.17 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.18 boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.19 power management system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.20 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.21 clock generation and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.22 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.23 identification register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.1.2 pad driver and pad classes su mmary . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table of contents
TC1762 table of contents preliminary data sheet 2 v1.0, 2008-04 4.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.2.2 analog to digital converter (adc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.2.3 fast analog to digital conv erter (fadc) . . . . . . . . . . . . . . . . . . . . . . . . .82 4.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 4.2.5 temperature sens or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.3.2 output rise/fall ti mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 4.3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 4.3.4 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 4.3.5 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 4.3.6 debug trace timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.3.7 timing for jtag signal s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 4.3.8 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.8.1 micro link interface (mli ) timing . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.8.2 micro second channel (msc) interfac e timing . . . . . . . . . . . . . . . .104 4.3.8.3 synchronous se rial channel (ssc) master mo de timing . . . . . . . . .105 5 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 5.4 quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
TC1762 summary of features preliminary data sheet 3 v1.0, 2008-04 1 summary of features the TC1762 has the following features: ? high-performance 32-bit super-scaler tricore v1.3 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 66 or 80 mhz operation at full temperature range ? multiple on-chip memories ? 32 kbyte local data memory (sram) ? 4 kbyte overlay memory ? 8 kbyte scratch-pad ram (spram) ? 8 kbyte instruction cache (icache) ? 1024 kbyte flash memory ? 16 kbyte data flash (2 kbyte eeprom emulation) ? 16 kbyte boot rom ? 8-channel dma controller ? fast-response interrupt system with 255 hardw are priority arbitration levels serviced by cpu ? high-performance on-chip bus structure ? 64-bit local memory bu s (lmb) to flash memory ? system peripheral bus (spb) for interconnectio ns of functional units ? versatile on-chip peripheral units ? two asynchronous/synchronous seri al channels (asc s) with baudrate generator, parity, framing an d overrun error detection ? one high speed synchronou s serial channel (ssc) with programmable data length and shift direction ? one micro second bus (msc) interface for serial port expansion to external power devices ? one high-speed micro link interface (mli) for serial inter-processor communication ? one multican module with two can n odes and 64 free assignable message objects for high efficien cy data handling via fifo buffering and gateway data transfer ? one general purpose timer array module (g pta) with a powerful set of digital signal filtering and ti mer functionality to real ize autonomous and complex input/output management ? one 16-channel analog -to-digital converter unit (adc) with selectable 8-bit, 10- bit, or 12-bit, supporti ng 32 input channels ? one 2-channel fast analog -to-digital converter unit (fadc) with concatenated comb filters for hardware data reducti on: supporting 10-bit resolution, with minimum conversion time of 262.5ns (@ 80 mhz) or 318.2ns (@ 66 mhz)
TC1762 summary of features preliminary data sheet 4 v1.0, 2008-04 ? 32 analog input lines for adc and fadc ? 81 digital general purpose i/o lines ? digital i/o ports with 3.3 v capability ? on-chip debug suppor t for ocds level 1 and 2 (cpu, dma) ? dedicated emulation device ch ip for multi-core debugging , tracing, and calibration via usb v1.1 interface available (tc1766ed) ? power management system ? clock generation unit with pll ? core supply vo ltage of 1.5 v ? i/o voltage of 3.3 v ? full automotive temperat ure range: -40 to +125c ? pg-lqfp-176-2 package
TC1762 summary of features preliminary data sheet 5 v1.0, 2008-04 ordering information the ordering code for infin eon microcontrollers provides an exact refe rence to the required product. this or dering code identifies: ? the derivative itself, i.e. its function set, the temper ature range, and the supply voltage ? the package and the type of delivery for the available ordering codes for the tc17 62, please refer to the ?product catalog microcontrollers? that su mmarizes all available microcontroller variants. this document describes the derivatives of the device.the table 1-1 enumerates these derivatives and summar izes the differences. table 1-1 TC1762 derivative synopsis derivative ambient temperature range sak-TC1762-128f66hl t a = -40 o c to +125 o c; 66 mhz operation frequency sak-TC1762-128f80hl t a = -40 o c to +125 o c; 80 mhz operation frequency
TC1762 general device information preliminary data sheet 6 v1.0, 2008-04 2 general device information chapter 2 provides the general in formation for the TC1762. 2.1 block diagram figure 2-1 shows the TC1762 block diagram. figure 2-1 TC1762 block diagram dma 8 ch. bi0 f fp i f cpu system peri phe ral bus (spb) ports sbcu mcb06056 mult i can (2 nodes, 64 buffer) stm ext. request unit lbcu lf i bridge ocds debug interface/jtag abbreviat ions: i cache: i nst ruct ion cache spram: scratch-pad ram ldram: local dat a ram o vram: o verlay ram brom: boot rom pf lash: program f lash df lash: dat a f lash lmb: local memory bus spb: system peripheral bus mli0 tricore (tc1.3m) pmi 8 kb spram 8 kb icache dmi 32 kb ldram cps 16 kb brom 1024 kb pf lash 16 kb dflash pmu gpta fpu asc1 asc0 mem check 4 kb o vram overlay me chan ism fadc 2 ch. adc0 32 ch. analog input assi gnme nt ssc0 dma bus pll scu pll local memory bus (lmb) bi1 smif msc0
TC1762 general device information preliminary data sheet 7 v1.0, 2008-04 2.2 logic symbol figure 2-2 shows the TC1762 logic symbol. figure 2-2 TC1762 logic symbol 8 7 9 fcln 0 fclp 0a testmode bypass nmi hdrst porst v ss msc0 control digital circuitry power supply general control sop0a son0 v dd v ddp an[35:0] adc analog inputs v ddm v ssm v ddmf v ssmf v ddaf v ssaf v aref0 v ag nd0 v faref v fagnd v ddf l3 adc/fadc analog power supply mcb06066 port 0 16-bit v ddo sc3 alternate functions brkout xtal1 xtal2 oscillator tdi tck trst port 1 15-bit port 2 14-bit port 3 16-bit port 4 4-bit gpta, scu gpta, adc ssc0, mli 0, gpta , msc 0 asc0/1, ssc0, scu, can tdo ocds / jtag control gpta, scu tms brkin trclk v ddo sc v ssosc port 5 16-bit gpta, ocds l 2, mli 0 TC1762
TC1762 general device information preliminary data sheet 8 v1.0, 2008-04 2.3 pin configuration figure 2-3 shows the TC1762 pin configuration. figure 2-3 TC1762 pinning for pg-lqfp-176-2 package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 39 40 41 42 43 44 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 30 31 32 33 34 35 36 37 38 45 46 47 48 49 50 51 52 53 97 96 95 94 93 92 91 90 89 100 99 98 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 p0.0/in0/swcfg0/out0/out56 p0.1/in1/swcfg1/out1/out57 p0.2/in2/swcfg2/out2/out58 p0.3/in3/swcfg3/out3/out59 p0.4/in4/swcfg4/out4/out60 p0.5/in5/swcfg5/out5/out61 p0.6/in6/swcfg6/req2/out6/out62 p0.7/in7/swcfg7/req3/out7/out63 p0.8/in8/swcfg8/out8/out64 p0.9/in9/swcfg9/out9/out65 p0.10/in10/swcfg10/out10/out66 p0.11/in11/swcfg11/out11/out67 p0.12/in12/swcfg12/out12/out68 p0.13/in13/swcfg13/out13/out69 p0.14/in14/swcfg14/req4/out14/out70 p0.15/in15/swcfg15/req5/out15/out71 p1.0/in16/out16/out72 p1.1/in17/out17/out73 p1.2/in18/out18/out74 p1.3/in19/out19/out75 p1.4/in20/emg_in/out20/out76 p1.5/in21/out21/out77 p1.6/in22/out22/out78 p1.7/in23/out23/out79 p1.8/in24/in48/out24/out48 p1.9/in25/in49/out25/out49 p1.10/in26/in50/out26/out50 p1.11/in27/in51/out27/out51 ad0emux0/p1.12 ad0emux1/p1.13 ad0emux2/p1.14 tclk0/out32/in32/p2.0 slso03/out33/tready0a/in33/p2.1 tvalid0a/out34/in34/p2.2 tdata0/out35/in35/p2.3 out36/rclk0a/in36/p2.4 rready0a/out37/in37/p2.5 out38/rvalid0a/in38/p2.6 out39/rdata0a/in39/p2.7 p2.8/slso04/en00 p2.9/slso05/en01 p2.10/gpio p2.11/fclp0b p2.12/sop0b p2.13/sdi0 p3.0/rxd0a p3.1/txd0a p3.2/sclk0 p3.3/mrst0 p3.4/mtsr0 p3.5/slso00/slso00 p3.6/slso01/slso01 p3.7/slsi0/slso02 p3.8/slso06/txd1a p3.9/rxd1a p3.10/req0 p3.11/req1 p3.12/rxdcan0/rxd0b p3.13/txdcan0/txd0b p3.14/rxdcan1/rxd1b p3.15/txdcan1/txd1b out52/out28/hwcfg0/in52/in28/p4.0 out53/out29/hwcfg1/in53/in29/p4.1 out54/out30/hwcfg2/in54/in30/p4.2 p4.3/in31/in55/out31/out55/sysclk ocdsdbg0/out40/in40/p5.0 ocdsdbg1/out41/in41/p5.1 ocdsdbg2/out42/in42/p5.2 ocdsdbg4/out44/in44/p5.4 ocdsdbg3/out43/in43/p5.3 ocdsdbg5/out45/in45/p5.5 ocdsdbg6/out46/in46/p5.6 ocdsdbg7/out47/in47/p5.7 ocdsdbg8/rdata0b/p5.8 ocdsdbg9/rvalid0b/p5.9 ocdsdbg10/rready0b/p5.10 ocdsdbg11/rclk0b/p5.11 ocdsdbg12/tdata0/p5.12 ocdsdbg13/tvalid0b/p5.13 ocdsdbg14/tready0b/p5.14 ocdsdbg15/tclk0/p5.15 fclp0a fcln0 sop0a son0 an0 an1 an2 an3 an4 an5 an6 an8 an7 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 an24 an25 an26 an27 an28 an29 an30 an31 an32 an33 an34 an35 trst tck tdi tdo tms brkin brkout nmi hdrst porst bypass testmode xtal1 xtal2 v dd v ddp v ss n.c. n.c. trclk TC1762 v dd v ddp v ss v ddmf v ssmf v ddaf v ssaf v faref v fagnd v ddm v ssm v aref0 v agnd0 v dd v ddp v ss v dd v ddp v ss v ss v dd v ddp v ss v ddosc v ddosc3 v ssosc v ddfl3 v ddp v ss v dd v ddp v ss v dd v ddp v ss mcp06067
TC1762 general device information preliminary data sheet 9 v1.0, 2008-04 2.4 pad driver and input classes overview the TC1762 provides different types and classes of input and output lines. for understanding of the abbreviations in table 2-1 starting at the next page, table 4-1 gives an overview on the pad type and class types.
TC1762 general device information preliminary data sheet 10 v1.0, 2008-04 2.5 pin definitions and functions table 2-1 shows the TC1762 pin def initions and functions. table 2-1 pin definiti ons and functions symbol pins i/o pad driver class power supply functions parallel ports p0 i/o a1 v ddp port 0 port 0 is a 16-bit bi -directional general- purpose i/o port which can be alternatively used for gpta i/o lines or external trigger inputs. p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 p0.12 p0.13 p0.14 p0.15 145 146 147 148 166 167 173 174 149 150 151 152 168 169 175 176 in0 / out0 / in1 / out1 / in2 / out2 / in3 / out3 / in4 / out4 / in5 / out5 / in6 / out6 / req2 in7 / out7 / req3 in8 / out8 / in9 / out9 / in10 / out10 / in11 / out11 / in12 / out12 / in13 / out13 / in14 / out14 / req4 in15 / out15 / req5 out56 line of gpta out57 line of gpta out58 line of gpta out59 line of gpta out60 line of gpta out61 line of gpta out62 line of gpta external trigger input 2 out63 line of gpta external trigger input 3 out64 line of gpta out65 line of gpta out66 line of gpta out67 line of gpta out68 line of gpta out69 line of gpta out70 line of gpta external trigger input 4 out71 line of gpta external trigger input 5 in addition, the state of the port pins are latched into the software configuration input register scu_sclir at the rising edge of hdrst . therefore, port 0 pins can be used for operating mode sele ctions by software.
TC1762 general device information preliminary data sheet 11 v1.0, 2008-04 p1 i/o v ddp port 1 port 1 is a 15-bit bi -directional general purpose i/o port which can be alternatively used for gpta i/o lines and adc0 interface. p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 91 92 93 98 107 108 109 110 94 95 96 97 73 72 71 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a1 a1 a1 in16 / out16 / in17 / out17 / in18 / out18 / in19 / out19 / in20 / out20 / in21 / out21 / in22 / out22 / in23 / out23 / in24 / out24 / in25 / out25 / in26 / out26 / in27 / out27 / ad0emux0 ad0emux1 ad0emux2 out72 line of gpta out73 line of gpta out74 line of gpta out75 line of gpta out76 line of gpta out77 line of gpta out78 line of gpta out79 line of gpta in48 / out48 line of gpta in49 / out49 line of gpta in50 / out50 line of gpta in51 / out51 line of gpta adc0 external multiplexer control output 0 adc0 external multiplexer control output 1 adc0 external multiplexer control output 2 in addition, p1.4 also serves as emergency shut-off input for certain i/o lines (e.g. gpta related outputs). table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 12 v1.0, 2008-04 p2 i/o v ddp port 2 port 2 is a 14-bit bi -directional general- purpose i/o port which can be alternatively used for gpta i/o, an d interface for mli0, msc0 or ssc0. p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 74 75 76 77 78 79 80 81 a2 a2 a2 a2 a1 a2 a1 a1 tclk0 in32 / out32 tready0a in33 / out33 slso03 tvalid0a in34 / out34 tdata0 in35 / out35 rclk0a in36 / out36 rready0a in37 / out37 rvalid0a in38 / out38 rdata0a in39 / out39 mli0 transmit channel clock output a line of gpta mli0 transmit channel ready input a line of gpta ssc0 slave select output 3 mli0 transmit channel valid output a line of gpta mli0 transmi t channel data output a line of gpta mli0 receive channel clock input a line of gpta mli0 receive channel ready output a line of gpta mli0 receive channel valid input a line of gpta mli0 receive channel data input a line of gpta table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 13 v1.0, 2008-04 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 164 160 161 162 163 165 a2 a2 a2 a2 a2 a1 slso04 en00 slso05 en01 fclp0b sop0b sdi0 ssc0 slave select output 4 msc0 enable output 0 ssc0 slave select output 5 msc0 enable output 1 msc0 clock output b msc0 serial data output b msc0 serial data input table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 14 v1.0, 2008-04 p3 i/o v ddp port 3 port 3 is a 16-bit bi -directional general- purpose i/o port which can be alternatively used for asc0/1, ssc0 and can lines. p3.0 p3.1 136 135 a2 a2 rxd0a txd0a asc0 receiver inp./outp. a asc0 transmitter output a this pin is sampled at the rising edge of porst . if this pin and the bypass input pin are both active, then o scillator bypass mode is entered. p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 129 130 132 126 127 131 128 138 137 144 143 142 134 133 a2 a2 a2 a2 a2 a2 a2 a2 a1 a1 a2 a2 a2 a2 sclk0 mrst0 mtsr0 slso00 slso01 slsi0 slso02 slso06 txd1a rxd1a req0 req1 rxdcan0 rxd0b txdcan0 txd0b rxdcan1 rxd1b txdcan1 txd1b ssc0 clock input/output ssc0 master receive input/ slave transmit output ssc0 master transmit output/slave receive input ssc0 slave select output 0 ssc0 slave select output 1 ssc0 slave select input ssc0 slave select output 2 ssc0 slave select output 6 asc1 transmitter output a asc1 receiver inp./outp. a external trigger input 0 external trigger input 1 can node 0 receiver input asc0 receiver inp./outp. b can node 0 transm. output asc0 transmitter output b can node 1 receiver input asc1 receiver inp./outp. b can node 1 transm. output asc1 transmitter output b table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 15 v1.0, 2008-04 p4 i/o v ddp port 4 / hardware configuration inputs p4.[3:0] hwcfg[3:0] boot mode and boot location inputs; inputs are latched with the rising edge of hdrst . during normal operation, port 4 pins may be used as alternate fu nctions for gpta or system clock output. p4.0 p4.1 p4.2 p4.3 86 87 88 90 a1 a1 a2 a2 in28 / out28 / in29 / out29 / in30 / out30 / in31 / out31 / sysclk in52 / out52 line of gpta in53 / out53 line of gpta in54 / out54 line of gpta in55 / out55 line of gpta system clock output table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 16 v1.0, 2008-04 p5 i/o a2 v ddp port 5 port 5 is a 16-bit bi -directional general- purpose i/o port. in emulat ion, it is used as a trace port for ocds lev el 2 debug lines. in normal operation, it is used for gpta i/o or the mli0 interface. p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 1 2 3 4 5 6 7 8 ocdsdbg0 in40 / out40 ocdsdbg1 in41 / out41 ocdsdbg2 in42 / out42 ocdsdbg3 in43 / out43 ocdsdbg4 in44 / out44 ocdsdbg5 in45 / out45 ocdsdbg6 in46 / out46 ocdsdbg7 in47 / out47 ocds l2 debug line 0 (pipeline status sig. ps0) line of gpta ocds l2 debug line 1 (pipeline status sig. ps1) line of gpta ocds l2 debug line 2 (pipeline status sig. ps2) line of gpta ocds l2 debug line 3 (pipeline status sig. ps3) line of gpta ocds l2 debug line 4 (pipeline status sig. ps4) line of gpta ocds l2 debug line 5 (break qualification line brk0) line of gpta ocds l2 debug line 6 (break qualification line brk1) line of gpta ocds l2 debug line 7 (break qualification line brk2) line of gpta table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 17 v1.0, 2008-04 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 13 14 15 16 17 18 19 20 ocdsdbg8 rdata0b ocdsdbg9 rvalid0b ocdsdbg10 rready0b ocdsdbg11 rclk0b ocdsdbg12 tdata0 ocdsdbg13 tvalid0b ocdsdbg14 tready0b ocdsdbg15 tclk0 ocds l2 debug line 8 (indirect pc addr. pc0) mli0 receive channel data input b ocds l2 debug line 9 (indirect pc addr. pc1) mli0 receive channel valid input b ocds l2 debug line 10 (indirect pc addr. pc2) mli0 receive channel ready output b ocds l2 debug line 11 (indirect pc addr. pc3) mli0 receive channel clock input b ocds l2 debug line 12 (indirect pc addr. pc04) mli0 transmi t channel data output b ocds l2 debug line 13 (indirect pc addr. pc05) mli0 transmit channel valid output b ocds l2 debug line 14 (indirect pc address pc6) mli0 transmit channel ready input b ocds l2 debug line 15 (indirect pc address pc7) mli0 transmit channel clock output b table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 18 v1.0, 2008-04 msc0 outputs fclp0a fcln0 sop0a son0 157 156 159 158 o o o o c v ddp lvds msc clock and data outputs 2) msc0 differential driver clock output positive a msc0 differential driver clock output negative msc0 differential driver serial data output positive a msc0 differential driver serial data output negative table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 19 v1.0, 2008-04 analog inputs an[35:0] an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 an24 an25 an26 an27 an28 an29 an30 67 66 65 64 63 62 61 36 60 59 58 57 56 55 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 id ? analog input port the analog input port provides altogether 36 analog input lines to adc0 and fadc. an[31:0]: adc0 ana log inputs [31:0] an[35:32]: fadc analog differential inputs analog input 0 analog input 1 analog input 2 analog input 3 analog input 4 analog input 5 analog input 6 analog input 7 analog input 8 analog input 9 analog input 10 analog input 11 analog input 12 analog input 13 analog input 14 analog input 15 analog input 16 analog input 17 analog input 18 analog input 19 analog input 20 analog input 21 analog input 22 analog input 23 analog input 24 analog input 25 analog input 26 analog input 27 analog input 28 analog input 29 analog input 30 table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 20 v1.0, 2008-04 an31 an32 an33 an34 an35 32 31 30 29 28 i d ? analog input 31 analog input 32 analog input 33 analog input 34 analog input 35 system i/o trst 114 i a2 1) v ddp jtag module reset/enable input tck 115 i a2 1) v ddp jtag module clock input tdi 111 i a1 1) v ddp jtag module serial data input tdo 113 o a2 v ddp jtag module serial data output tms 112 i a2 1) v ddp jtag module state ma chine control input brkin 117 i/o a3 v ddp ocds break input (alternate output) 2)3) brk out 116 i/o a3 v ddp ocds break output (alternate input) 2)3) trclk 9oa4 v ddp trace clock for ocds_l2 lines 2) nmi 120 i a2 4)5) v ddp non-maskable in terrupt input hdrst 122 i/o a2 6) v ddp hardware reset input / reset indication output porst 7) 121 i a2 4) v ddp power-on reset input bypass 119 i a1 1) v ddp pll clock bypass select input this input has to be held stable during power- on resets. with bypass = 1, the spike filters in the hdrst , porst and nmi inputs are switched off. test mode 118 i a2 4)8) v ddp test mode select input for normal operation of the TC1762, this pin should be connecte d to high level. xtal1 xtal2 102 103 i o n.a. v ddosc oscillator/pll/clock generator input/output pins n.c. 21, 89 ?? ? not connected these pins are reserved for future extension and must not be co nnected externally. table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 21 v1.0, 2008-04 power supplies v ddm 54 ? ? ? adc analog part powe r supply (3.3 v) v ssm 53 ? ? ? adc analog part ground for v ddm v ddmf 24 ? ? ? fadc analog part power supply (3.3 v) v ssmf 25 ? ? ? fadc analog part ground for v ddmf v ddaf 23 ? ? ? fadc analog part logic power supply (1.5 v) v ssaf 22 ? ? ? fadc analog part logic ground for v ddaf v aref0 52 ? ? ? adc reference voltage v agnd0 51 ? ? ? adc reference ground v faref 26 ? ? ? fadc reference voltage v fagnd 27 ? ? ? fadc reference ground v ddosc 105 ? ? ? main oscillator and pll power supply (1.5 v) v ddosc3 106 ? ? ? main oscillator powe r supply (3.3 v) v ssosc 104 ? ? ? main oscillator and pll ground v ddfl3 141 ? ? ? power supply for flash (3.3 v) v dd 10, 68, 84, 99, 123, 153, 170 ?? ? core power supply (1.5 v) table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 22 v1.0, 2008-04 v ddp 11, 69, 83, 100, 124, 154, 171, 139 ?? ? port power supply (3.3 v) v ss 12, 70, 85, 101, 125, 155, 172, 140, 82 ?? ? ground 1) these pads are i/o pads with input only function. its input characteristics are identical with the input characteristics as defined for class a pads. 2) in case of a power-fail condition (one or more pow er supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 3) programmed by software as either break input or break output. 4) these pads are input only pads with input characteristics. 5) input only pads with input spike filter. 6) open drain pad with input spike filter. 7) the dual input reset system of TC1762/tc1766ed, assumes that the porst reset pin is used for power-on reset only. it has to be taken into account that if a system uses the porst reset input for other system resets, the emulation part of the tc1766ed emulation device is reset as well. thus, it will always force a complete re-initialization of the emulator and will prevent the user debugging across these types of resets. 8) input only pads without input spike filter. table 2-1 pin definiti ons and functions (cont?d) symbol pins i/o pad driver class power supply functions
TC1762 general device information preliminary data sheet 23 v1.0, 2008-04 table 2-2 list of pull-up/pull-do wn reset behavi or of the pins pins porst =0 porst =1 all gpios, tdi , tms , tdo pull-up hdrst drive-low pull-up bypass pull-up high-impedance trst , tck high-impedance pull-down trclk high-impedance brkin , brkout , testmode pull-up nmi , porst pull-down
TC1762 functional description preliminary data sheet 24 v1.0, 2008-04 3 functional description chapter 3 provides an overview of the TC1762 functional description. 3.1 system architecture and on-chip bus systems the TC1762 has two i ndependent on-chip buses (see also TC1762 block diagram on page 2-6 ): ? local memory bus (lmb) ? system periphe ral bus (spb) the lmb bus connects the cpu local resources for data and instructio n fetch. the local memory bus interconnects t he memory units and functiona l units, such as cpu and pmu. the main target of the lmb bus is to support device s with fast response times, optimized for speed. this al lows the dmi and pmi fast access to local memory and reduces load on the fpi bus. the tricore system itself is located on lmb bus. the local memory bus is a syn chronous, pipelined, split bu s with variable block size transfer support. it supports 8- , 16-, 32- and 64-bit singl e transactions and variable length 64-bit block transfers. the spb bus is accessible to the cpu via th e lmb bus bridge. t he system peripheral bus (spb bus) in TC1762 is an on-chip fpi bus. the fpi bus interconnects the functional units of the tc 1762, such as the dm a and on-chip peripheral components. the fpi bus is designed to be quick to be acquired by on -chip functional un its, and quick to transfer data. the low setu p overhead of the fpi bus a ccess protocol guarantees fast fpi bus acquisition, which is required for time-critica l applications.the fpi bus is designed to sustain high transf er rates. for example, a peak transfer rate of up to 320 mbyte/s can be achieved with a 80 mhz bus clock and 32-bi t data bus. with a 66 mhz bus clock, the peak transfer rate is up to 264 mbytes/s. mu ltiple data transfers per bus arbitration cycle allow the fpi bus to operate at cl ose to its peak bandwidth. both the lmb bus and the spb bus runs at full cpu speed. t he maximum cpu speed is 66 or 80 mhz depending on the derivative. additionally, two simplified bus interfaces ar e connected to and controlled by the dma controller: ?dma bus ? smif interface
TC1762 functional description preliminary data sheet 25 v1.0, 2008-04 3.2 on-chip memories as shown in the TC1762 block diagram on page 2-6 , some of the TC1762 units provide on-chip memories that are used as program or data memory. ? program memory in pmu ? 16 kbyte boot rom (brom) ? 1024 kbyte program flash (pflash) ? program memory in pmi ? 8 kbyte scratch-pad ram (spram) ? 8 kbyte instruction cache (icache) ? data memory in pmu ? 16 kbyte data flash (dflash) ? 4 kbyte overlay ram (ovram) ? data memory in dmi ? 32 kbyte local data ram (ldram) ? on-chip sram with par ity error protection features of program flash ? 1024 kbyte on-chip program flash memory ? usable for instruction code or constant data storage ? 256-byte program interface ? 256 bytes are programmed into pf lash page in one step/command ? 256-bit read interface ? transfer from pflash to cpu/pmi by four 64-bit single cycle burst transfers ? dynamic correction of single-b it errors duri ng read access ? detection of double-bit errors ? fixed sector architecture ? eight 16 kbyte, one 12 8 kbyte, one 256 kbyte a nd one 512 kbyte sectors ? each sector separately erasable ? each sector separately write-protectable ? configurable read protecti on for complete pflash wit h sophisticated read access supervision, combined with write protection for complete pflash (protection against ?trojan horse? software) ? configurable write pr otection for each sector ? each sector separately write-protectable ? with capability to be re-programmed ? with capability to be lo cked forever (otp) ? password mechanism for temporary disabling of write and read protection ? on-chip generation of programming voltage ? jedec-standard based command sequences for pflash control ? write state machine controls programming and erase operations ? status and error reporting by status flags and interrupt ? margin check for detection of problematic pflash bits
TC1762 functional description preliminary data sheet 26 v1.0, 2008-04 features of data flash ? 16 kbyte on-chip data flash memory , organized in tw o 8 kbyte banks ? usable for data storage wit h eeprom functionality ? 128 byte of pr ogram interface ? 128 bytes are programmed into one dflash page by one step/command ? 64-bit read interface (no burst transfers) ? dynamic correction of single-b it errors duri ng read access ? detection of double-bit errors ? fixed sector architecture ? two 8 kbyte banks/sectors ? each sector separately erasable ? configurable read protecti on (combined with write prot ection) for complete dflash together with pflash read protection ? password mechanism for temporary disabling of write and read protection ? erasing/programm ing of one bank possible while reading data from the other bank ? programming of one ban k while erasing the other bank possible ? on-chip generation of programming voltage ? jedec-standard based command sequences for dflash control ? write state machine controls programming and erase operations ? status and error reporting by status flags and interrupt ? margin check for detection of problematic dflash bits
TC1762 functional description preliminary data sheet 27 v1.0, 2008-04 3.3 architectural address map table 3-1 shows the overall archit ectural address map as defi ned for the tricore and as implemented in TC1762. table 3-1 TC1762 archit ectural address map seg- ment contents size description 0-7 global 8 x 256 mbyte reserved (mmu space); cached 8 global memory 256 mbyte reserved (246 mbyte); pmu, boot rom; cached 9 global memory 256 mbyte fpi space; cached 10 global memory 256 mbyte reserved (246 mbyt e), pmu, boot rom; non- cached 11 global memory 256 mbyte fpi space; non-cached 12 local lmb memory 256 mbyte reserved; bottom 4 mbyte visible from fpi bus in segment 14; cached 13 dmi 64 mbyte local data memory ram; non-cached pmi 64 mbyte local code memory ram; non-cached ext_per 96 mbyte reserved; non-cached ext_emu 16 mbyte reserved; non-cached bootrom 16 mbyte b oot rom space, boot rom mirror; non-cached 14 extper 128 mbyte reserved; non-speculative; non- cached; no execution cpu[0 ..15] image region 16 x 8 mbyte non-speculative; non- cached; no execution 15 lmb_per csfrs int_per 256 mbyte csfrs of cpus[0 ..15]; lmb & fpi peripheral space; non-speculative; non-cached; no execution
TC1762 functional description preliminary data sheet 28 v1.0, 2008-04 3.4 memory protection system the TC1762 memory protection system spec ifies the addressabl e range and read/write permissions of memory segments available to the current execut ing task. the memory protection system controls the position a nd range of addressable segments in memory. it also controls the types of read and write operations allo wed within addressable memory segments. any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate trap service ro utine (tsr) to handle the error. thus, the memory prot ection system protects critical system functions against both software and hardware errors. the memory protection hardware can also generate signals to the debug unit to facilita te tracing illegal memory accesses. there are two memory protec tion register sets in the TC1762, numbered 0 and 1, which specify memory prot ection ranges and permissi ons for code and data. the psw.prs bit field determines wh ich of these is the set curre ntly in use by the cpu. as the TC1762 uses a harvard-style memory architecture, each memory protection register set is broken down into a data pr otection register set and a code protection register set. each data prot ection register set can specif y up to four address ranges to receive a particular protec tion modes. each code protec tion register set can specify up to two address ranges to receiv e a particular protection modes. each data protection register sets and code protection register sets determines the range and protection modes for a separate memory area. each set contains a pair of registers which determine th e address range (the data segment protection registers and code segment protection registers) and one register (data protection mode register) which determines th e memory access modes that applies to the specified range.
TC1762 functional description preliminary data sheet 29 v1.0, 2008-04 3.5 dma controller and memory checker the dma controller of the TC1762 transfers data from data source locations to data destination locations without intervention of the cpu or other on-chip devices. one data move operation is controll ed by one dma channel. eight dma channels are provided in one dma sub-block. t he bus switch pr ovides the connection of the dma sub-block to the two fpi bus interfaces and an mli bu s interface. in the TC1762, the fpi bus interfaces are connected to the system peripheral bus and the dma bus. the third specific bus interface provides a connection to the micro li nk interface module (mli0 in the TC1762) and other dma-re lated devices (memory che cker module in the TC1762). clock control, address decoding, dma request wiring, and dma interrupt service request control are implementation-specific and managed outside the dm a controller kernel. figure 3-1 shows the implementation details and interconnections of the dma module. figure 3-1 dma contro ller block diagram features ? 8 independent dma channels interrupt request nodes mcb06149 clock control f dma sr[15:0] dma controller arbiter/ switch control bus switch fpi bus interface 0 fpi bus inte rface 1 mli interf ac e memory checker mli0 system periphera bus dma bus dma requests of on-chip periph. units address decoder dma interrupt control ch0n_out dma channels 00-07 dma sub-block 0 request selection/ arbitration transaction control unit
TC1762 functional description preliminary data sheet 30 v1.0, 2008-04 ? 8 dma channels in the dma sub-block ? up to 8 selectable reque st inputs per dma channel ? 2-level programmable priority of dma channels within the dma sub-block ? software and hard ware dma request ? hardware requests by selected on-c hip peripherals and external inputs ? programmable priority of the dma sub-blocks on the bus interfaces ? buffer capability for move actions on the buses (at le ast 1 move per bus is buffered). ? individually programm able operation modes for each dma channel ? single mode: stops and disables dma c hannel after a predefined number of dma transfers ? continuous mode: dma channel remain s enabled after a predefined number of dma transfers; dma tran saction can be repeated. ? programmable address modification ? full 32-bit addressing capab ility of each dma channel ? 4 gbyte address range ? support of circular buffer addressing mode ? programmable data width of dma transfer/transaction: 8-bit, 16-bit, or 32-bit ? micro link bus interface support ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt g eneration (the servic e request node logic fo r the mli channels is also implemented in the dma module) ? all buses connected to the dma module must work at the same frequency. ? read/write requests of the system bus si de to the peripherals on dma bus are bridged to the dma bus (onl y the dma is the master on the dma bus), allowing easy access to these peripherals by cpu memory checker the memory checker module (mchk) makes it possible to check the data consistency of memories. any spb bus master may access th e memory checker. it is preferable the dma does it as described her eafter. it uses dma 8-bit, 16-bit, or 32-bit moves to read from the selected address ar ea and to write t he value read in a me mory checker input register. with each write ope ration to the memory checker input register, a polynomial checksum calculation is trigger ed and the result of the ca lculation is stored in the memory checker re sult register. the memory checker uses the standard ethernet polynom ial, which is given by: g 32 = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 note: although the polynomial a bove is used for generation, the generation algorithm differs from the one that is used by the et hernet protocol.
TC1762 functional description preliminary data sheet 31 v1.0, 2008-04 3.6 interrupt system the TC1762 interrupt system provides a flexib le and time-efficient means of processing interrupts. an interrupt reque st is serviced by the cpu, which is called the ?service provider?. interrupt requests are called ?service reques ts? rather than ?interrupt requests? in th is document. each peripheral in the tc176 2 can generate service request s. additionally, the bus control units, the debug uni t, and even the cpu itself c an generate service requests to the service provider. as shown in figure 3-2 , each TC1762 unit that can generate service requests is connected to one or multip le service request nodes (s rn). each srn contains a service request control register mod_srcx, where ?mod? is the identifier of the service requesting unit and ?x ? an optional index. the cp u interrupt arbitration bus connects the srns wi th the interrupt control unit (icu), which arbitrates service requests for the cpu and administer s the cpu interrupt arbitration bus. the debug unit can gen erate service requests to th e cpu. the cpu makes service requests directly to itself (via the icu) . the cpu service request nodes are activated through software. depending on the selected system clock frequency f sys , the number of f sys clock cycles per arbitration cycle must be selected as follows: ? f sys < 60 mhz: icr.conecyc = 1 ? f sys > 60 mhz: icr.conecyc = 0
TC1762 functional description preliminary data sheet 32 v1.0, 2008-04 figure 3-2 block diagram of the TC1762 interrupt system service req. nodes service req. nodes service requestors cpu interrupt control unit inte rrup t service provider mca06181 4 srns 4 mli0 3 srns 3 ssc0 4 srns 4 asc0 4 srns asc1 6 srns multican 4 srns adc0 2 srns fadc 38 srns 38 gp ta 0 cpu in terrup t arbitration bus in t. req. pipn cpu ccpn in t. a ck. software and breakpoint interrupts icu 2 srns 2 msc0 1 srn 1 srn 1 srn 1 srn 4 srns e xt. int stm fpu flash service requestors lbcu sbcu cerberus dma 2 srns 1 srn 1 srn 2 srns dma bus 4 6 4 2 2 1 1 2 2 1 1 2 38 2 4 6 4 4 3 4 1 1 4 1 1 1 1 4 1 1 2 cpu interrupt control unit 5 srns 5 5
TC1762 functional description preliminary data sheet 33 v1.0, 2008-04 3.7 asynchronous/synchronous se rial interfaces (asc0, asc1) figure 3-3 shows a global view of the functiona l blocks and interf aces of the two asynchronous/synchronous serial interfaces, asc0 and asc1. figure 3-3 block diagram of the asc interfaces the asc provides serial communic ation between the TC1762 and other microcontrollers, microprocesso rs, or external peripherals. the asc supports full-duplex asynch ronous communicat ion and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock that is gener ated by the asc intern ally. in asynchronous mode, 8-bit or 9-bit data tr ansfer, parity generation, and the number of stop bits can be mcb06211c asc0 module (kernel) port 3 control asc1 module (kernel) p3.12 / rxd0b p3.13 / txd0b p3.0 / rxd0a p3.1 / txd0a p3.14 / rxd1b p3.15 / txd1b p3.9 / rxd1a p3.8 / txd1a rxd_i1 rxd_o rxd_i0 txd_o rxd_i1 rxd_o rxd_i0 txd_o in terru pt control eir tbir tir rir clock control address decoder in terru pt control f asc eir tbir tir rir to dma asc0_rdr asc0_tdr to dma asc1_rdr asc1_tdr a2 a2 a2 a2 a2 a2 a2 a2
TC1762 functional description preliminary data sheet 34 v1.0, 2008-04 selected. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data is double- buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. test ing is supported by a loop-back opt ion. a 13-bit baud rate generator provides the asc with a separate serial cl ock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. features ? full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity-bit generation/checking ? one or two stop bits ? baud rate from 5.0 mbit/s to 1.19 bit/s (@ 80 mhz mo dule clock) and 4.1mbit/s to 0.98 bit/s (@ 66 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability ? half-duplex 8-bit synch ronous operating mode ? baud rate from 10.0 mbit/s to 813.8 bit/s (@ 80 mhz module clock) and 8.25 mbit/s to 671.4 bit/s (@ 66 mhz module clock) ? double-buffered transmitter/receiver ? interrupt generation ? on a transmit buffer empty condition ? on a transmit last bi t of a frame condition ? on a receive buffer full condition ? on an error condition (frame, parity, overrun error)
TC1762 functional description preliminary data sheet 35 v1.0, 2008-04 3.8 high-speed synchronous serial interface (ssc0) figure 3-4 shows a global view of the functional blocks and interfaces of the high-speed synchronous serial interface, ssc0. figure 3-4 block diagra m of the ssc interfaces the ssc supports full-duplex and half-duplex serial synchronous communication up to 40.0 mbaud at 80 mhz module cl ock and up to 33 mbaud at 66 mhz module clock. the serial clock signal can be ge nerated by the ssc itself (m aster mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. th is allows communication with spi-compatible devices. transmission and reception of data is double -buffered. a shift clock generator provides the ssc with a separate serial clock signal. se ven slave select inputs are available for clock control address decoder interrupt control f ssc 0 ssc0_tdr eir tir rir port 3 control ssc0 module (kernel ) mrstb mtsr master slsi1 slso[2:0] mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master f clc0 slsi[7:2] 1) enable 1) m/s select 1) 1) these lines are not connected port 2 control slso[5:3] slso6 slso7 1) ssc0_rdr to dma mcb06225 p3.3 /mrst0 p3.4 /mtsr0 p3.2 /sclk0 p3.7 /slsi0 p2.8 /slso04 p2.9 /slso05 p2.1 /slso03 a2 a2 a2 a2 a2 a2 a2 p3 .7 /slso02 p3 .5 /slso00 p3 .8 /slso06 a2 a2 a2 p3 .6 /slso01 a2
TC1762 functional description preliminary data sheet 36 v1.0, 2008-04 slave mode operation. eight programmable slave select outputs (chip selects) are supported in master mode. features ? master and slave mode operation ? full-duplex or ha lf-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift directi on: lsb or msb shift first ? programmable clock polarity: idle low or idle high state for the shift clock ? programmable clock/data phase: data shif t with leading or trai ling edge of the shift clock ? baud rate generati on from 40.0 mbit/s to 610.36 bit/s (@ 80 mhz module clock) and 503.5 bit/s to 33 mbit/s (@ 66 mhz module clock) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, p hase, baud rate, transmit error) ? flexible ssc pin configuration ? seven slave select inputs slsi[7:1] in slave mode ? eight programmable slave select outputs slso[7:0] in master mode ? automatic slso generation with programmable timing ? programmable active level and enable control
TC1762 functional description preliminary data sheet 37 v1.0, 2008-04 3.9 micro second bus interface (msc0) the msc interface provides a serial communication link ty pically used to connect power switches or other pe ripheral devices. the serial co mmunication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. figure 3-5 shows a global view of the msc interface signals. figure 3-5 block diagram of the msc interfaces the downstream and upstream channels of the msc module communicate with the external world via nine i/o lines. eight output lines are required for the serial communication of the downstre am channel (clock, data, an d enable signals). one out of eight input lines sdi[7:0] is us ed as serial data input sign al for the upstream channel. the source of the serial data to be transmitted by the downstream cha nnel can be msc register contents or data that is provided at the altinl/a ltinh input lines. these input lines are typically connected to other on-chip peripheral unit s (for example with a timer unit like the gpta). an emergen cy stop input signal makes it possible to set bits of the serial data stream to dedica ted values in emergency cases. msc0 module (kernel) mca0625 5 port 2 control p2.13 / sdi0 en0 sop son0 son sop0a p2.9 / en01 p2.8 / en00 fcln0 fcln fclp0a fclp en1 p2.11 / fclp0 b p2.12 / sop0b upstream channel downstream channel clock control address decoder interrupt control sr[1:0] emgstopmsc altinl[15:0] altinh[15:0] to dma sr[3:2] (from gpta) (from scu) f msc0 f clc0 sr15 (from can) sdi[0] 1) 1) sdi[7:1] are connected to high level 16 16 c c c c a2 a2 a2 a2 a1
TC1762 functional description preliminary data sheet 38 v1.0, 2008-04 clock control, address decoding, and inte rrupt service request control are managed outside the msc module kernel. service request outputs are able to trigger an interrupt or a dma request. features ? fast synchronous serial inte rface to connect power switch es in particular, or other peripheral devices via serial buses ? high-speed synchronous serial tr ansmission on down stream channel ? serial output clock frequency: f fcl = f msc /2 ? fractional clock divider for precis e frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-cont rolled, timer-controlled, or free-running ? programmable upstream data fr ame length (16 or 12 bits) ? transmission with or without sel bit ? flexible chip select generation indicate s status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 4, 8, 16, 32, 64, 128, or 256 ? standard asynchronous serial frames ? parity error checker ? 8-to-1 input multip lexer for sdi lines ? built-in spike fi lter on sdi lines
TC1762 functional description preliminary data sheet 39 v1.0, 2008-04 3.10 multican controller (can) figure 3-6 shows a global view of the multican module with its functional blocks and interfaces. figure 3-6 block diagra m of multican module the multican module contains two ind ependently-operating ca n nodes with full-can functionality that are able to exchange data and remote frames via a gateway function. transmission and reception of can fram es is handled in accordance with can specification v2.0 b (active). each can node can receive and tr ansmit standard frames with 11-bit ident ifiers as well as extended frames with 29-bit identifiers. both can nodes share a common set of mess age objects. each me ssage object can be individually allocated to o ne of the can nodes. besides se rving as a storage container for incoming and outgoing frames , message objects can be co mbined to build gateways between the can n odes or to setup a fifo buffer. the message objects are organi zed in double-chained linke d lists, where each can node has its own list of mess age objects. a can node stores frames only into message objects that are allocated to the message object list of the can node, and it transmits only messages belonging to this message ob ject list. a powerful, command-driven list controller performs all messa ge object list operations. the bit timings for the ca n nodes are derived from the module timer clock ( f can ), and are programmable up to a data rate of 1 mbit/s. external bus transceivers are connected to a can node via a pair of receive and transmit pins. multican module kernel mca0628 1 interrupt control f can port 3 control can control message object buffer 64 objects txdc0 rxdc0 txdc1 rxdc1 linked list control p3.15 / txdcan 1 p3.14 / rxdcan 1 p3.13 / txdcan 0 p3.12 / rxdcan 0 f clc clock control address decoder dma int_o [1:0] int_o15 int_o [5:2] can node 0 can node 1 a2 a2 a2 a2
TC1762 functional description preliminary data sheet 40 v1.0, 2008-04 multican features ? can functionality conforms to can specif ication v2.0 b active for each can node (compliant to iso 11898) ? two independent can nodes ? 64 independent message objects (shared by the can nodes) ? dedicated control regi sters for each can node ? data transfer rate up to 1mbit/s, individually pr ogrammable for each node ? flexible and powerful me ssage transfer control and error handling capabilities ? full-can functionality: messa ge objects can be individually ? assigned to one of the two can nodes ? configured as transmit or receive object ? configured as message bu ffer with fifo algorithm ? configured to handle frames with 11-bit or 29-bit identifiers ? provided with programmable accept ance mask register for filtering ? monitored via a frame counter ? configured for remote monitoring mode ? automatic gateway mode support ? 6 individually programmable interrupt nodes ? can analyzer mode for bus monitoring
TC1762 functional description preliminary data sheet 41 v1.0, 2008-04 3.11 micro link serial bus interface (mli0) the micro link interface is a fast synchrono us serial interface that allows data exchange between microcontrollers of the 32-bit audo microcontroller family withou t intervention of a cpu or other bus masters. figure 3-7 shows how two microcontrollers are typically connected together via their ml i interface. the mli operates in both microcontrollers as a bus master on the system bus. figure 3-7 typical micro li nk interface connection features ? synchronous serial commun ication between mli transmi tters and mli receivers located on the same or on di fferent microcontroller devices ? automatic data transfer/request transact ions between local/remote controller ? fully transparent read/ write access supported (= remote programming) ? complete address range of re mote controller available ? specific frame protocol to tr ansfer commands, addresses and data ? error control by parity bit ? 32-bit, 16-bit, and 8-bit data transfers ? programmable baud rates ? mli transmitter baud rate: max. f mli /2 (= 40 mbit/s @ 80 mhz module clock) ? mli receiver baud rate: max. f mli ? multiple remote (slave) controllers ar e supported mli transmitter and mli receiv er communicate with other off-chip mli receivers and mli transmitters via a 4-line serial i/o bus each. several i/o lines of these i/o buses are available outside the mli module kernel as four- line output or input buses. mca06061 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory
TC1762 functional description preliminary data sheet 42 v1.0, 2008-04 figure 3-8 shows a global view of the functi onal blocks of the mli module with its interfaces. figure 3-8 block diagra m of the mli module s r[3 :0 ] f ml i0 address decoder interrupt control clock control to dma s r[4 :7 ] port 2 control p2.1 / tready0a treadya tclk treadyd tvalida tvalidd tdata transmitter receiver rclka rclkd rreadya rreadyd rvalida rvalidd rdataa rdatab treadyb rreadyb rvalidb rdatad tvalidb rclkb mli 0 module (kernel ) mcb06322 p2.0 / tclk0 p5.14 / tready0b p2.2 / tvalid0a p2.3 / tdata0 p2.4 / rclk0a p2.5 / rready0a p2.6 / rvalid0a p2.7 / rdata0a p5.11 / rclk0b p5.9 / rvalid0b p5.8 / rdata0b p5.10 / rready0b p5.13 / tvalid0b port 5 control p5.15 / tclk0 p5.12 / tdata0 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a1 a1 a1 brkout cerberus
TC1762 functional description preliminary data sheet 43 v1.0, 2008-04 3.12 general purpose timer array the gpta provides a set of timer, compare, a nd capture functional ities that can be flexibly combined to form signal measurement and signa l generation units. they are optimized for tasks typical of engine, gearbox, electrical motor control applications, but can also be used to generate simple and complex signal wavefo rms needed in other industrial applications. the TC1762 contains one general purpose timer array (gpta0). figure 3-9 shows a global view of the gpta module. figure 3-9 block diagra m of the gpta module signal generation unit mcb06063 gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 clock bus gpta clock generation unit cloc k con n. clock distribution unit f gpta ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 i/o line sharing unit interrupt sharing unit
TC1762 functional description preliminary data sheet 44 v1.0, 2008-04 3.12.1 functionality of gpta0 the general purpose timer array gpta0 prov ides a set of hardware modules required for high-speed digital signal processing: ? filter and prescaler cells (f pc) support input noise filt ering and prescaler operation. ? phase discrimination logic units (pdl) decod e the direction inform ation output by a rotation tracking system. ? duty cycle measurement cells (dcm ) provide pulse-width measurement capabilities. ? a digital phase locked loop unit (pll) generates a programm able number of gpta module clock ticks during an input signal?s period. ? global timer units (gt) driven by various clock sources are im plemented to operate as a time base for the as sociated global timer cells. ? global timer cells (gtc) can be programmed to capt ure the content s of a global timer on an external or internal event. a gt c may also be used to control an external port pin depending on the result of an internal compare operation. gtcs can be logically concatenated to pr ovide a common ex ternal port pin with a complex signal waveform. ? local timer cells (ltc) operat ing in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various extern al or internal events. input lines can be s hared by an ltc and a gtc to trig ger their programmed operation simultaneously. the following list summarizes the spec ific features of the gpta unit. clock generation unit ? filter and prescaler cell (fpc) ? six independent units ? three basic operating modes: prescaler, delayed debounce f ilter, immediate debounce filter ? selectable input sources: port lines, gpta module clock, fpc output of preceding fpc cell ? selectable input clocks: gpta module clock, prescaled gpta modu le clock, dcm clo ck, compensated or uncompensated pll clock ? f gpta /2 maximum input signal fr equency in filter modes ? phase discriminator logic (pdl) ? two independent units ? two operating modes (2- and 3-sensor signals) ? f gpta /4 maximum input signal fr equency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode
TC1762 functional description preliminary data sheet 45 v1.0, 2008-04 ? duty cycle measurement (dcm) ? four independent units ? 0 - 100% margin and time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ? one unit ? arbitrary multiplicati on factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution unit (cdu) ? one unit ? provides nine clock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation unit ? global timers (gt) ? two independent units ? two operating modes (free-running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global time r cell (gtc) ? 32 units related to the global timers ? two operating modes (capture, co mpare and captur e after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) ? 64 independent units ? three basic operating modes (timer , capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt control unit ? 111 interrupt sources, genera ting up to 38 service requests
TC1762 functional description preliminary data sheet 46 v1.0, 2008-04 i/o sharing unit ? interconnecting inputs and outp uts from internal clocks, fpc, gtc, ltc, ports, and msc interface
TC1762 functional description preliminary data sheet 47 v1.0, 2008-04 3.13 analog-to-digital converter (adc0) section 3.13 shows the global view of the a dc module with its functional blocks and interfaces and the f eatures which are provided by the module. figure 3-10 block diag ram of the adc module the adc module has 16 analog inpu t channels. an analog mult iplexer selects the input line for the analog input channels from among 32 analog inputs. addi tionally, an external analog multiplexer can be used for analog input extensio n. external clock control, address decoding, and service request (interrupt) cont rol are managed outside the adc module kernel. external tri gger conditions are controlled by an external request unit. this unit generates the contro l signals for auto-scan contro l (asgt), software trigger control (sw0tr, sw0gt), the event trigger cont rol (etr, egt), q ueue control (qtr, qgt), and timer trigger control (ttr, tgt). an automatic self-calibrati on adjusts the adc module to changing temperatures or process variations. figure 3-10 shows the global view of the adc module with its functional blocks and interfaces. adc0 module kernel interrupt control clock control address decoder f adc to dma ain16 analog multiplexer mca0642 7 v agnd0 v dd v ss v ddm v aref0 v ssm group 1 p1.13 /ad0emux1 p1.12 /ad0emux0 an0 an15 an16 f clc port 1 control ain0 ain15 group 0 asgt sw0tr, sw0gt etr, egt qtr, qgt ttr, tgt external request unit (scu) ain30 from gpta from ports from msc0 p1.14 / ad0emux2 (grps ) an30 ain31 an31 die temperature measurement scu_con.dtson 0 1 gprs emux0 emux1 8 2 6 sr[3:0] sr[7:4] a1 a1 a1 d d d d d
TC1762 functional description preliminary data sheet 48 v1.0, 2008-04 features ? 8-bit, 10-bit, 12- bit a/d conversion ? conversion time below 2.5 s @ 10-bit resolution ? extended channel status in formation on request source ? successive approximat ion conversion method ? total unadjusted error (tue) of 2 lsb @ 10-bit resolution ? integrated sample & hold functionality ? direct control of up to 16 analog input channels ? dedicated control and status registers for each analog channel ? powerful conversion request sources ? selectable reference vo ltages for each channel ? programmable sample and c onversion timing schemes ? limit checking ? flexible adc module serv ice request control unit ? automatic control of ex ternal analog multiplexers ? equidistant samples initiated by timer ? external trigger and gating i nputs for conversion requests ? power reduction and clock control feature ? on-chip die temperature sens or output voltage measurement
TC1762 functional description preliminary data sheet 49 v1.0, 2008-04 3.14 fast analog-to-digita l converter unit (fadc) the on-chip fadc module of the TC1762 basically is a 2-cha nnel a/d converter with 10- bit resolution that operates by the method of the successive approximation. as shown in figure 3-11 , the main fadc functional blocks are: ? the input stage ? con tains the differential inputs and the programm able amplifier ? the a/d converter ? is responsible for the analog-to- digital conversion ? the data reduction unit ? contains prog rammable antialiasing and data reduction filters ? the channel trigger control block ? dete rmines the trigger and gating conditions for the two fadc channels ? the channel timers ? can independently trigger the conversion of each fadc channel ? the a/d control block is responsible for the overall fadc functionality the fadc module is supplied by the followin g power supply and refe rence voltage lines: ? v ddmf / v ddmf :fadc analog part po wer supply (3.3 v) ? v ddaf / v ddaf :fadc analog part logic power supply (1.5 v) ? v faref / v fagnd :fadc reference voltage (3.3 v)/fadc refe rence ground
TC1762 functional description preliminary data sheet 50 v1.0, 2008-04 figure 3-11 block diagra m of the fadc module features ? extreme fast conver sion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz and 318.2 ns @ f fadc =66 mhz) ? 10-bit a/d conversion ? higher resolution by averaging of co nsecutive conversions is supported ? successive approximat ion conversion method ? two differential input channels ? offset and gain calibrati on support for each channel ? differential input amplifier with programmabl e gain of 1, 2, 4 and 8 for each channel ? free-running (channel timers) or triggered conversion modes ? trigger and gatin g control for ex ternal signals ? built-in channel timers for internal triggering ? channel timer request pe riods independently select able for each channel clock control address decoder mca0644 5 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control an32 ts[7:0] gs[7:0] f fadc f clc sr[1:0] fain0p fain0n fain1p fain1n an33 an34 an35 p3.10 / req 0 external request unit (scu) p3.11 / req 1 p0.14 / req 4 p0.15 / req 5 gpta0 out1 out9 out18 out26 out2 out10 out19 out27 pdout2 pdout3 dma sr[3:2] fadc module kernel d d d d a1 a1 a1 a1
TC1762 functional description preliminary data sheet 51 v1.0, 2008-04 ? selectable, programmable anti-aliasi ng and data reduction filter block 3.15 system timer the TC1762?s stm is designed for global system timing applications requiring both high precision and long period. features ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit porti ons of the 56-bit counte r can be read synchronously ? flexible interrupt generation based on compare match with partial stm content ? driven by maximum 66 or 80 mhz (= f sys , default after reset = f sys /2) depending on derivative ? counting starts automatica lly after a reset operation ? stm is reset by: ? watchdog reset ? software reset (rst_req.rrstm must be set) ? power-on reset ? stm (and clock divider stm_clc.rmc) is not reset at a hardware reset (hdrst = 0) ? stm can be halted in debug/susp end mode (via stm_clc register) the stm is an upward co unter, running either at the system clock frequency f sys or at a fraction of it. the st m clock frequency is f stm = f sys /rmc with rmc = 0-7 (default after reset is f stm = f sys /2, selected by rmc = 010 b) . rmc is a bit field in register stm_clc. in case of a power-on reset, a watchdog reset, or a software reset, the stm is reset. after one of these reset conditions, the stm is e nabled and immediately starts counting up. it is not possible to affect the content of t he timer during normal op eration of the TC1762. the timer registers can only be read but not written to. the stm can be optionally di sabled for power-saving pur poses, or suspended for debugging purposes via its cl ock control register. in suspend mode of the TC1762 (initiated by writing an appropriate val ue to stm_clc register ), the stm clock is stopped but all register s are still readable. due to the 56-bit widt h of the stm, it is not possible to read it s entire content with one instruction. it needs to be r ead with two lo ad instructions. since the timer would continue to count between the two load op erations, there is a chance t hat the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). to enable a synchro nous and consistent reading operation of the stm content, a capture register (stm_cap) is implemented. it latches the content of the high part of the stm each time when one of the regi sters stm_tim0 to stm_tim5 is read. thus, stm_cap holds the upper value of the timer at exactly the
TC1762 functional description preliminary data sheet 52 v1.0, 2008-04 same time when the lower part is read. t he second read operatio n would then read the content of the stm_cap to get the complete timer value. the stm can also be read in sections from seven r egisters, stm_tim0 through stm_tim6, that select increa singly higher-order 32-bit r anges of the stm. these can be viewed as individual 32-bit timers, each wit h a different resoluti on and timing range. the content of the 56-bit system timer can be compar ed with the content of two compare values stored in the stm_cmp0 and stm_cmp1 registers. interrupts can be generated on a compare match of the stm with the stm_cmp0 or stm_cmp1 registers. the maximum clock period is 2 56 f stm . at f stm = 80 mhz, for exampl e, the stm counts 28.56 years before over flowing. thus, it is capable of timing the entire expect ed product life-time of a syst em without overfl owing continuously. figure 3-12 shows an overview on the system ti mer with the options for reading parts of the stm contents.
TC1762 functional description preliminary data sheet 53 v1.0, 2008-04 figure 3-12 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 56-bit system timer address decoder clock control mcb06185 compare register 0 interrupt control compare register1 porst stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 enable / disable f stm stmir1 stmir0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0
TC1762 functional description preliminary data sheet 54 v1.0, 2008-04 3.16 watchdog timer the wdt provides a highly relia ble and secure way to detect and recover from software or hardware failure. the wdt helps to abort an accidental malfunction of the TC1762 in a user-specified time period. when enabled , the wdt will cause the TC1762 system to be reset if the wdt is not serviced within a user-programmable time period. the cpu must service the wdt within this time in terval to prevent t he wdt from causing a TC1762 system reset. h ence, routine service of the wd t confirms that the system is functioning as expected. in addition to this standard ?watchdog? function, the wdt incorporates the end-of- initialization (endinit) featur e and monitors its modifica tions. a system-wide line is connected to the wdt_con0.endinit bit, serv ing as an additional write-protection for critical registers (besides s upervisor mode protection). regi sters protected via this line can only be modified wh en supervisor mode is acti ve and bit endinit = 0. a further enhancement in the TC1762?s wdt is its reset prewarni ng operation. instead of resetting the device upon th e detection of an error immediately (t he way that standard watchdogs do), the wdt first issues a non-maskable interru pt (nmi) to the cpu before resetting the device at a specif ied time period later. this step gives the cpu a chance to save the system state to t he memory for later investig ation of the cause of the malfunction; an impo rtant aid in debugging. features ? 16-bit watchdog counter ? selectable input frequency: f sys /256 or f sys /16384 ? 16-bit user-definable reload value for norm al watchdog operation, fixed reload value for time-out and prewarning modes ? incorporation of the endinit bit and monitoring of its modifications ? sophisticated password access mechanism with fixed and user-definable password fields ? proper access always requires two writ e accesses. the time between the two accesses is monitored by the wdt and is limited. ? access error detection: invalid password ( during first access) or invalid guard bits (during second access) trigger the watchdog re set generation ? overflow error detection: an overflow of the counte r triggers the watchdog reset generation. ? watchdog function c an be disabled; access protection and endinit monitor function remain enabled. ? double reset detection: if a watchdog indu ced reset occurs twice, a severe system malfunction is assumed and the TC1762 is held in reset until a power-on or hardware reset occurs. this prevents the device from being periodically re set if, for instance, connection to the external memory has been lost such that system initialization could not even be performed.
TC1762 functional description preliminary data sheet 55 v1.0, 2008-04 ? important debugging suppor t is provided through the re set prewarning operation by first issuing an nmi to the cpu before fina lly resetting the device after a certain period of time. 3.17 system control unit the system control unit (scu) of the TC1762 handles several system control tasks. the system control ta sks of the scu are: ? clock system sele ction and control ? reset and boot operation control ? power management control ? configuration input sampling ? external request unit ? system clock output control ? on-chip sram parity control ? pad driver temperatur e compensatio n control ? emergency stop input co ntrol for gpta outputs ? gpta input in1 control ? pad test mode contro l for dedicated pins ? odcs level 2 trace control ? nmi control ? miscellaneous scu control
TC1762 functional description preliminary data sheet 56 v1.0, 2008-04 3.18 boot options the TC1762 booting schemes prov ide a number of different bo ot options for the start of code execution. table 3-2 shows the boot options available in the TC1762. table 3-2 TC1762 boot selections brkin hwcfg [3:0] testmode type of boot bootrom exit jump address normal boot options 1 0000 b 1 enter bootstrap loader mode 1: serial asc0 boot via asc0 pins d400 0000 h 0001 b enter bootstrap loader mode 2: serial can boot via p3.12 and p3.13 pins 0010 b start from internal pflash a000 0000 h 0011 b alternate boot mode (abm): start from internal pflash after crc check is correctly executed; enter a serial bootst rap loader mode 1) if crc check fails 1) the type of the alternate bootstrap loader mode is sele cted by the value of the scu_sclir.swopt[2:0] bit field, which contains the levels of the p0.[2:0] latched in with the rising edge of the hdrst. defined in abm header or d400 0000 h 1111 b enter bootstrap loader mode 3: serial asc0 boot via p3.12 and p3.13 pins d400 0000 h others reserved; execute stop loop ? debug boot options 0 0000 b 1 tri-state chip ? others irrel. reserved; execute stop loop ?
TC1762 functional description preliminary data sheet 57 v1.0, 2008-04 3.19 power management system the TC1762 power management system allows software to conf igure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there ar e three power management modes: ? run mode ? idle mode ? sleep mode the operation of each system component in each of thes e states can be configured by software. the power-managem ent modes provide flex ible reduction of power consumption through a combin ation of techniques, includ ing stopping the cpu clock, stopping the clocks of other system com ponents individually, and individually clock- speed reduction of some peripheral components. besides these explicit software-controlled power-saving modes, sp ecial attention has been paid to automatic power-s aving in those operating un its which are not required at a certain point of time, or idle in the TC1762. in that case, they are shut off automatically until their operatio n is required again. table 3-3 describes the features of the power management modes. in typical operation, idle mode and sleep mode may be entered and exited frequently during the run time of an applic ation. for example, system so ftware will typically cause the cpu to enter idle mode each time it has to wait for an interrupt before continuing its tasks. in sleep mode and idle mode, wake-u p is performed auto matically when any table 3-3 power manage ment mode summary mode description run the system is fully opera tional. all clocks and pe ripherals are enabled, as determined by software. idle the cpu clock is disabled, waiting for a condition to return it to run mode. idle mode can be entered by software when the processor has no active tasks to perform. all peripherals remain powered and clocked. processor memory is accessible to peripherals. a reset, watchdog timer event, a fa lling edge on the nmi pin, or any enabl ed interrupt event will return the sys tem to run mode. sleep the system clock signal is dist ributed only to those peripherals programmed to operate in sleep mode. the other peripheral module will be shut down by the suspend signa l. interrupts from operating peripherals, the watchdog time r, a falling edge on the nmi pin, or a reset event will return the system to run mode. entering this state requires an orderly shut-down co ntrolled by the power management state machine.
TC1762 functional description preliminary data sheet 58 v1.0, 2008-04 enabled interrupt signal is detected, or when the c ount value (wdt_sr.wdttim) changes from 7fff h to 8000 h . 3.20 on-chip debug support figure 3-13 shows a block diagram of the TC1762 ocds system. figure 3-13 ocds system block diagram the TC1762 basically supports three levels of debug operation: ? ocds level 1 debug support ? ocds level 2 debug support ? ocds level 3 debug support mcb06195 enable, control and reset ocds l1 dma syst em pe rip h era l bu s spb peripheral unit 1 spb peripheral unit n b reak an d s uspe nd si gna ls bcu tricore ocds l1 ocds l2 watch- dog timer jdi debug i/f jtag controller mcbs break switch cerberus os cu dma l2 brkin tdi tdo brkout trst tms tck ocds2[15:0] 16 multiplexer
TC1762 functional description preliminary data sheet 59 v1.0, 2008-04 ocds level 1 debug support the ocds level 1 debu g support is mainly assigned fo r real-time soft ware debugging purposes which have a demand for low-cost standard debugger hardware. the ocds level 1 is based on a jtag interface that is used by the external debug hardware to communicate wit h the system. the on -chip cerberus module controls the interactions between the jt ag interface and the on-chip modules. the ex ternal debug hardware may become master of the internal buses, and read or write the on-chip register/memory resources. the cerberus also makes it possible to define breakpoint and trigger conditions as we ll as to control us er program execution (run/stop, break, single-step). ocds level 2 debug support the ocds level 2 debug sup port makes it possible to implement program tracing capabilities for enhanced d ebuggers by extending the ocds level 1 debug functionality with an additional 16-bit wide tr ace output port with trace clo ck. with the trace extension, the following four trace capabilities are provid ed (only one of the three trace capabilities can be selected at a time): ? trace of the cpu program flow ? trace of the dma contro ller transaction requests ? trace of the dma controller move engine status information ocds level 3 debug support the ocds level 3 debug supp ort is based on a special tc 1766 emulation device, the tc1766ed, which provides additional features required for high-end emulation purposes. the tc1766ed is a device whic h includes the tc1766 product chip and additional emulation extensi on hardware in a package with the same footprint as the tc1766.
TC1762 functional description preliminary data sheet 60 v1.0, 2008-04 3.21 clock generation and pll the TC1762 clock system perfo rms the following functions: ? acquires and buffers incoming clock sig nals to create a ma ster clock frequency ? distributes in-phase synchronized clock si gnals throughout the tc 1762?s entire clock tree ? divides a system master clock frequency into lower frequencies required by the different modules for operation. ? dynamically reduces power consumption during operation of functional units ? statically reduces power consumption through progra mmable power-saving modes ? reduces electromagnetic interference (emi) by switching off unused modules the clock system must be o perational before the TC1762 c an function, so it contains special logic to handle power -up and reset operatio ns. its services are fundamental to the operation of the entire system, so it contains special fail-safe logic. features ? pll operation for multiplying clo ck source by different factors ? direct drive capability for direct clocking ? comfortable state machine for secure switching betw een basic pll, direct or prescaler operation ? sleep and power-down mode support the TC1762 clock generation unit (cgu) as shown in figure 3-14 allows a very flexible clock generation. it ba sically consists of an main oscillator circuit and a phase- locked loop (pll). the pll ca n converts a low-frequency exte rnal clock signal from the oscillator circuit to a high-speed in ternal clock for ma ximum performance. the system clock f sys is generated from an oscillator clock f osc in either o ne of the four hardware/software selectable ways: ? direct drive mode (pll bypass) : in direct drive mode, the tc17 62 clock system is directly dr iven by an external clock signal. input, i.e. f cpu = f osc and f sys = f osc . this allows operatio n of the TC1762 with a reasonably small fun damental mode crystal. ? vco bypass mode (prescaler mode) : in vco bypass mode, f cpu and f sys are derived from f osc by the two divider stages, p-divider and k-divider . the system clock f sys is equal to f cpu . ? pll mode: in pll mode, the pll is running. the vco clock f vco is derived from f osc , divided by the p factor, multiplied by the pl l (n-divider). the clock signals f cpu and f sys are derived from f vco by the k-divider . the system clock f sys is equal to f cpu . ? pll base mode : in pll base mode, the pll is ru nning at its vco base frequency and f cpu and f sys
TC1762 functional description preliminary data sheet 61 v1.0, 2008-04 are derived from f vco only by the k-divider. in this mode, the system clock f sys is equal to f cpu . figure 3-14 clock generation unit recommended oscillator circuits the oscillator circuit, a pierce oscillator, is designed to work with bot h, an external crystal oscillator or an external stable clock source. it basically consists of an inverting amplifier and a feedback element with xtal 1 as input, and xtal2 as output. when using a crystal, a proper external oscillator circuitr y must be con nected to both pins, xtal1 and xtal2. th e crystal frequency can be within the range of 4 mhz to 25 mhz. additionally, it is necessary to have two load capacitances c x1 and c x2 , and depending on the crystal ty pe, a series resistor r x2 , to limit the current. a test resistor r q may be temporarily inserted to measure the oscillation allo wance (negative resistance) of the oscillator circuitry. r q values are typically specifie d by the crystal vendor. the c x1 and c x2 values shown in figure 3-15 can be used as starti ng points for the negative resistance evaluation and for non-producti ve systems. the exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together wit h the crystal vendor using the negative resistance method. system control unit (scu) clock generation unit (cgu) pll 1:1 divider m u x m u x k:1 divider mca06083 oscillator circuit x tal1 x tal2 f osc phase detect. vco n divider f vco 1 0 f sys lock detector oscr pll_ lock ndiv [6:0] vco_ bypass kdiv [3:0] pll_ bypass register pll_clc vco_ sel[1:0] f cpu sys fsl p divi- der pdiv [2:0] osc disc register osc_con mosc ogc bypass osc_ bypass 1 osc. run detect.
TC1762 functional description preliminary data sheet 62 v1.0, 2008-04 oscillation measurement with the final target system is st rongly recommended to verify the input amplitude at xtal1 and to determ ine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. when using an external clock si gnal, the signal must be co nnected to xtal1. xtal2 is left open (unconnect ed). the external clock frequency can be in the range of 0 - 40 mhz if the pll is bypassed, and 4 - 40 mhz if the pll is used. the oscillator can also be us ed in combination with a ceramic re sonator. the final circuitry must also be verifi ed by the res onator vendor. figure 3-15 shows the recommended external oscill ator circuitries fo r both operating modes, external crystal mode and extern al input clock mode. a block capacitor is recommended to be placed between v ddosc / v ddosc3 and v ssosc . figure 3-15 oscillat or circuitries note: for crystal operation, it is st rongly recommended to measure the negative resistance in the final target system (lay out) to determine t he optimum parameters for the oscillator operation. please refer to the mini mum and maximum values of the negative resistance specif ied by the crystal supplier. TC1762 oscillator TC1762 osc illator mcs06084 v ddosc v ssosc c x1 4 - 25 mhz c x2 xtal1 xtal2 v ddosc v ssosc xtal1 xtal2 external clock signal f os c f os c fundamental mode crystal 4 - 40 mhz v ddosc3 v ddosc3 crystal frequency c x1 , c x2 1) 4 mhz 8 mhz 12 mhz 16 - 25 mhz 10 pf 12 pf 18 pf 33 pf 1) not e t hat t hese are evaluat ion st art values! r x2 1) 0 0 0 0 r x2 r q
TC1762 functional description preliminary data sheet 63 v1.0, 2008-04 3.22 power supply the TC1762 has several po wer supply lines for di fferent voltage classes: ? 1.5 v: core logic, oscillator and a/d converter supply ? 3.3 v: i/o ports, flash memories, oscillator, and a/d converter supply with reference voltages figure 3-16 shows the power supply concept of the TC1762 with the power supply pins and its connections to the functional units. figure 3-16 power supply concept of TC1762 TC1762 TC1762 pwrsupply core fl as h memori es v dd (1.5 v) 7 pll osc 3 1 v ddf l 3 3.3 v fadc v ddaf (1.5v) v ssaf v ddmf (3.3v) v ssmf 2 2 v faref (3.3v) v fagnd 2 v ssa 1 ports 8 v ddp (3.3 v) v ss 9 adc v ddm (3.3v) v ssm 2 v aref (3.3v) v agnd 2 v dda (1.5 v) 1 v ddo sc3 (3.3 v) v ddo sc (1.5 v) v ssosc
TC1762 functional description preliminary data sheet 64 v1.0, 2008-04 3.23 identification register values table 3-4 shows the address map and reset values of th e TC1762 identification registers. table 3-4 TC1762 identification registers short name address reset value stepping scu_ id f000 0008 h 002c c002 h - manid f000 0070 h 0000 1820 h - chipid f000 0074 h 0000 8b02 h - rtid f000 0078 h 0000 0001 h aa-step 0000 0011 h ab-step 0000 0007 h ac-step sbcu_id f000 0108 h 0000 6a0a h - stm_id f000 0208 h 0000 c006 h - cbs_ jdpid f000 0408 h 0000 6307 h - msc0_ id f000 0808 h 0028 c001 h - asc0_ id f000 0a08 h 0000 4402 h - asc1_ id f000 0b08 h 0000 4402 h - gpta0_ id f000 1808 h 0029 c004 h - dma_id f000 3c08 h 001a c012 h - can_id f000 4008 h 002b c012 h - ssc0_ id f010 0108 h 0000 4510 h - fadc_ id f010 0308 h 0027 c012 h - adc0_id f010 0408 h 0030 c001 h - mli0_ id f010 c008 h 0025 c006 h - mchk_ id f010 c208 h 001b c001 h - cps_id f7e0 ff08 h 0015 c006 h - cpu_id f7e1 fe18 h 000a c005 h - pmu_id f800 0508 h 002e c012 h - flash_id f800 2008 h 0041 c002 h - dmi_id f87f fc08 h 0008 c004 h - pmi_id f87f fd08 h 000b c004 h -
TC1762 functional description preliminary data sheet 65 v1.0, 2008-04 lbcu_id f87f fe08 h 000f c005 h - lfi_id f87f ff08 h 000c c005 h - table 3-4 TC1762 identification registers short name address reset value stepping
TC1762 electrical parameters preliminary data sheet 66 v1.0, 2008-04 4 electrical parameters chapter 4 provides the characteristics of the electrical par ameters which are implementation-specific for the TC1762. 4.1 general parameters the general parameters are described here to aid the us ers in interpreting the parameters mainly in section 4.2 and section 4.3 . the absolute maximum ratings and its operating conditions are provided fo r the appropriate sett ing in the TC1762. 4.1.1 parameter interpretation the parameters listed in this section partly repr esent the characteri stics of the TC1762 and partly its requirements on the system. to aid interpre ting the parameters easily when evaluating them for a design, they ar e marked with an two- letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the TC1762 and must be re garded for a system design. ? sr such paramete rs indicate s ystem r equirements which must provided by the microcontroller system in wh ich the TC1762 designed in.
TC1762 electrical parameters preliminary data sheet 67 v1.0, 2008-04 4.1.2 pad driver and pad classes summary this section gives an overview on the di fferent pad driver cl asses and its basic characteristics. more details (ma inly dc parameters) are defined in section 4.2.1 . table 4-1 pad driver an d pad classes overview class power supply type sub class speed grade load leakage 1) 1) values are for t jmax =150c. termination a 3.3v lvttl i/o, lvttl outputs a1 (e.g. gpio) 6 mhz 100 pf 500 na no a2 (e.g. serial i/os) 40 mhz 50 pf 6 aseries termination recommended a3 (e.g. brkin, brkout) 66 or 80 mhz 2) 2) this value corresponds to the operating frequency of the device, which depending on the derivative, can be 66 or 80 mhz. 50 pf 6 aseries termination recommended (for f > 25 mhz) a4 (e.g. trace clock) 66 or 80 mhz 2) 25 pf 6 aseries termination recommended c 3.3v lvds ? 50 mhz ? parallel termination 3) , 100 ? 10% 3) in applications where the lvds pins are not used (d isabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 ? 10%. d ? analog inputs, refe rence voltage inputs
TC1762 electrical parameters preliminary data sheet 68 v1.0, 2008-04 4.1.3 absolute maximum ratings table 4-2 shows the absolute maximum rati ngs of the tc17 62 parameters. note: stresses above thos e listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other condition s above those indicated in the operational sections of th is specification is not impl ied. exposure to absolute table 4-2 absolute maxi mum rating parameters parameter symbol limit values unit notes min. max. ambient temperature t a sr -40 125 c under bias storage temperature t st sr -65 150 c? junction temperature t j sr -40 150 c under bias voltage at 1.5 v power supply pins with respect to v ss 1) 1) applicable for v dd , v ddosc , v ddpll , and v ddaf . v dd sr ? 2.25 v ? voltage at 3.3 v power supply pins with respect to v ss 2) 2) applicable for v ddp , v ddfl3, v ddm , and v ddmf . v ddp sr ? 3.75 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.5 v ddp + 0.5 or max. 3.7 vwhatever is lower voltage on any class d analog input pin with respect to v agnd v ain, v arefx sr -0.5 v ddm + 0.5 or max. 3.7 vwhatever is lower voltage on any class d analog input pin with respect to v ssaf v ainf, v faref sr -0.5 v ddmf + 0.5 or max. 3.7 vwhatever is lower cpu & lmb bus frequency 3)4) 3) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. 4) this value depend on the derivative and the operating frequency it is designated for. for a device operating at 66 mhz, the absolute maximum frequency is also 66 mhz. similarly, for a device operating at 80 mhz, the absolute maximum frequency is 80 mhz. f cpu sr ? 66 or 80 mhz ? fpi bus frequency 3)4) f sys sr ? 66 or 80 mhz 5) 5) the ratio between f cpu and f sys is fixed at 1:1.
TC1762 electrical parameters preliminary data sheet 69 v1.0, 2008-04 maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > related v dd or v in < v ss ) the voltage on the related v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. 4.1.4 operating conditions the following operating conditi ons must not be exceeded in order to ensure correct operation of the TC1762. all parameters specified in the following table refer to these operating conditions, unless otherwise noted. table 4-3 operating condition parameters parameter symbol limit values unit notes conditions min. max. digital supply voltage 1) v dd v ddosc sr 1.42 1.58 2) v? v ddp v ddosc3 sr 3.13 3.47 3) v for class a pins (3.3v 5%) v ddfl3 sr 3.13 3.47 3) v? digital ground voltage v ss sr 0 v ? ambient temperature under bias t a sr -40 +125 c? analog supply volta ges ? ? ? ? see separate specification page 4-75 , page 4-82 cpu clock f cpu sr ? 4) 80 5) mhz ? short circuit current i sc sr -5 +5 ma 6) absolute sum of short circuit currents of a pin group (see table 4-4 ) | i sc | sr ? 20 ma see note 7) absolute sum of short circuit currents of the device | i sc | sr ? 100 ma see note 7)
TC1762 electrical parameters preliminary data sheet 70 v1.0, 2008-04 inactive device pin current (v dd =v ddp =0) i id sr -1 1 ma voltage on all power supply pins v ddx =0 external load capacitance c l sr ? see dc chara cterist ics pf depending on pin class 1) digital supply voltages applied to the TC1762 must be static regulated voltages which allow a typical voltage swing of 5%. 2) voltage overshoot up to 1.7 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) voltage overshoot to 4 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) the TC1762 uses a static design, so the minimum operation frequency is 0 mhz. due to test time restriction no lower frequency boundary is tested, however. 5) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. 6) applicable for digital outputs. 7) see additional document ?tc1796 pin reliability in overload? for overload current definitions. table 4-3 operating condition parameters parameter symbol limit values unit notes conditions min. max.
TC1762 electrical parameters preliminary data sheet 71 v1.0, 2008-04 table 4-4 pin groups for overload/sho rt-circuit current sum parameter group pins 1 trclk, p5.[7:0], p0 .[7:6], p0.[15:14] 2 p0.[13:12], p0.[5:4], p2.[13:8], sop0a, son0, fclp0a, fcln0 3 p0.[11:8], p0.[3:0], p3.[13:11] 4 p3[10:0], p3.[15:14] 5 hdrst , porst , nmi , testmode , brkin , brkout , bypass, tck, trst , tdo, tms, tdi, p1.[7:4] 6 p1.[3:0], p1.[11:8], p4.[3:0] 7 p2.[7:0], p1.[14:12] 8 p5.[15:8]
TC1762 electrical parameters preliminary data sheet 72 v1.0, 2008-04 4.2 dc parameters the electrical characteristics of the dc parameters are detaile d in this section. 4.2.1 input/output pins table 4-5 provides the characteristics of the input/output pins of the TC1762. table 4-5 input/output dc-characteristics (operating conditions apply) parameter symbol limit values unit test conditions min. max. general parameters pull-up current 1) | i puh |cc10 100 a v in < v ihamin ; class a1/a2/input pads. 20 200 a v in < v ihamin ; class a3/a4 pads. pull-down current 1) | i pdl |cc10 150 a v in > v ilamax ; class a1/a2/input pads. 20 200 a v in > v ilamax ; class a3/a4 pads. pin capacitance 1) (digital i/o) c io cc ? 10 pf f = 1 mhz t a = 25 c input only pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) input low voltage class a1/a2 pins v ila sr -0.3 0.34 v ddp v? input high voltage class a1/a2 pins v iha sr 0.64 v ddp v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? input low voltage class a3 pins v ila3 sr ? 0.8 v ? input high voltage class a3 pins v iha3 sr 2.0 ? v ? input hysteresis hysa cc 0.1 v ddp ?v 2)5) input leakage current i ozi cc ? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 3)
TC1762 electrical parameters preliminary data sheet 73 v1.0, 2008-04 class a pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage 4) v ola cc ? 0.4 v i ol = 2 ma for strong driver mode, (not applicable to class a1 pins) i ol = 1.8 ma for medium driver mode, a2 pads i ol = 1.4 ma for medium driver mode, a1 pads i ol =370 a for weak driver mode output high voltage 3) v oha cc 2.4 ? v i oh = -2 ma for strong driver mode, (not applicable to class a1 pins) i oh = -1.8 ma for medium driver mode, a1/a2 pads i oh = -370 a for weak driver mode v ddp - 0.4 ?v i oh = -1.4 ma for strong driver mode, (not applicable to class a1 pins) i oh = -1 ma for medium driver mode, a1/a2 pads i oh = -280 a for weak driver mode input low voltage class a1/2 pins v ila sr -0.3 0.34 v ddp v? input high voltage class a1/2 pins v iha sr 0.64 v ddp v ddp + 0.3 or 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? input hysteresis hysa cc 0.1 v ddp ?v 2)5) table 4-5 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol limit values unit test conditions min. max.
TC1762 electrical parameters preliminary data sheet 74 v1.0, 2008-04 input leakage current class a2/3/4 pins i oza24 cc ? 3000 6000 na (( v ddp /2)-1) < v in <(( v ddp /2)+1) otherwise 3) input leakage current class a1 pins i oza1 cc ? 500 na 0 v < v in < v ddp class c pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage v ol cc 815 mv parallel termination 100 ? 1% output high voltage v oh cc 1545 mv output differential voltage v od cc 150 600 mv output offset voltage v os cc 1075 1325 mv output impedance r 0 cc 40 140 ? class d pads see adc characteristics ? ? ? ? 1) not subject to production test, verified by design / characterization. 2) the pads that have spike filter function in the input path: porst , hdrst , nmi do not have hysteresis. 3) only one of these parameters is tested, the other is verified by design characterization 4) max. resistance between pin and next power supply pin 25 ? for strong driver mode (verified by design characterization). 5) function verified by design, value is not subject to production test - verified by design/characterization. hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot be guaranteed that it suppresses switching due to external system noise. table 4-5 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol limit values unit test conditions min. max.
TC1762 electrical parameters preliminary data sheet 75 v1.0, 2008-04 4.2.2 analog to digital converter (adc0) table 4-6 provides the characteristics of the adc module in the TC1762. table 4-6 adc characteristics (operating conditions apply) parameter symbol limit valu es unit test conditions / remarks min. typ. max. analog supply voltage v ddm sr 3.13 3.3 3.47 1) v? v dd sr 1.42 1.5 1.58 2) v power supply for adc digital part, internal supply analog ground voltage v ssm sr -0.1 ? 0.1 v ? analog reference voltage 17) v arefx sr v agndx + 1v v ddm v ddm + 0.05 1) 3)4) v? analog reference ground 17) v agndx sr v ssmx - 0.05v 0 v aref - 1 v v? analog reference voltage range 5)17) v arefx - v agndx sr v ddm /2 v ddm + 0.05 analog input voltage range v ain sr v agndx ?v arefx v? v ddm supply current i ddm sr 2.5 4 ma rms 6) power-up calibration time t puc cc ? ? 3840 f adc clk ? internal adc clocks f bc cc 2 ? 40 mhz f bc = f ana 4 f ana cc 0.5 ? 10 mhz f ana = f bc /4 sample time t s cc 4 (chconn.stc +2) t bc s? 8 t bc ?? s
TC1762 electrical parameters preliminary data sheet 76 v1.0, 2008-04 conversion time t c cc t s +40 t bc +2 t div s for 8-bit conversion t s +48 t bc +2 t div s for 10-bit conversion t s +56 t bc +2 t div s for 12-bit conversion total unadjusted error 4) tue 7) cc ? ? 1 lsb for 8-bit conv. ?? 2 lsb for 10-bit conv. ?? 4 lsb for 12-bit conv. 8)9) ?? 8 lsb for 12-bit conv. 10)9) dnl error 11)5) tue dnl cc ? 1.5 3.0 lsb for 12-bit conv. 12) 9) inl error 11)5) tue inl cc ? 1.5 3.0 lsb for 12-bit conv. 12) 9) gain error 11)5) tue gain cc ? 0.5 3.5 lsb for 12-bit conv. 12) 9) offset error 11)5) tue off cc ? 1.0 4.0 lsb for 12-bit conv. 12) 9) input leakage current at analog inputs an0, an1 and an31. see figure 4-3 13) i oz1 14) cc ?1000 ? 300 na (0% v ddm ) < v in < (2% v ddm ) ?200 4 00 na (2% v ddm ) < v in < (95% v ddm ) ?200 1000 na (95% v ddm ) < v in < (98% v ddm ) ?200 3000 na (98% v ddm ) < v in < (100% v ddm ) table 4-6 adc characteristics (cont?d) (operating cond itions apply) parameter symbol limit valu es unit test conditions / remarks min. typ. max.
TC1762 electrical parameters preliminary data sheet 77 v1.0, 2008-04 input leakage current at analog inputs an2 to an30, see figure 4-3 i oz1 14) cc ?1000 ? 200 na (0% v ddm ) < v in < (2% v ddm ) ?200 300 na (2% v ddm ) < v in < (95% v ddm ) ?200 1000 na (95% v ddm ) < v in < (98% v ddm ) ?200 3000 na (98% v ddm ) < v in < (100% v ddm ) input leakage current at v aref i oz2 cc ? ? 1 a0v< v aref < v ddm, no conversion running input current at v aref 17) i aref cc ? 35 75 a rms 0v< v aref < v ddm 15) total capacitance of the voltage reference inputs 16)17) c areftot cc ? ? 25 pf 9) switched capacitance at the positive reference voltage input 17) c arefsw cc ? 15 20 pf 9)18) resistance of the reference voltage input path 16) r aref cc ? 1 1.5 k ? 500 ohm increased for an[1:0] used as reference input 9) total capacitance of the analog inputs 16) c aintot cc ? ? 25 pf 6)9) switched capacitance at the analog voltage inputs c ainsw cc ? ? 7 pf 9)19) table 4-6 adc characteristics (cont?d) (operating cond itions apply) parameter symbol limit valu es unit test conditions / remarks min. typ. max.
TC1762 electrical parameters preliminary data sheet 78 v1.0, 2008-04 on resistance of the transmission gates in the analog voltage path r ain cc ? 1 1.5 k ? 9) on resistance for the adc test (pull-down for ain7) r ain7t cc 200 300 1000 ? test feature available only for ain7 9) current through resistance for the adc test (pull- down for ain7) i ain7t cc ? 15 rms 30 peak ma test feature available only for ain7 9) 1) voltage overshoot to 4 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) voltage overshoot to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) if the reference voltage v aref increases or the v ddm decreases, so that v aref =( v ddm + 0.05 v to v ddm + 0.07 v), then the accuracy of the adc decreases by 4lsb12. 5) if a reduced reference voltage in a range of v ddm /2 to v ddm is used, then the adc converter errors increase. if the reference voltage is reduced with the factor k (k<1), then tue, dnl, inl gain and offset errors increase with the factor 1/k. if a reduced reference voltage in a range of 1 v to v ddm /2 is used, then there are additional decrease in the adc speed and accuracy. 6) current peaks of up to 6 ma with a duration of max. 2 ns may occur 7) tue is tested at v aref =3.3v, v agnd = 0 v and v ddm =3.3v 8) adc module capability. 9) not subject to production test, verified by design / characterization. 10) value under typical application conditions due to integration (switching noise, etc.). 11) the sum of dnl/inl/gain/offset errors does not exceed the related tue total unadjusted error. 12) for 10-bit conversions the dnl/inl/gain/offset error values must be multiplied with factor 0.25. for 8-bit conversions the dnl/inl/gain/offset error values must be multiplied with 0.0625. 13) the leakage current definition is a continuous function, as shown in figure 4-3 . the numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 14) only one of these parameters is tested, the other is verified by design characterization. table 4-6 adc characteristics (cont?d) (operating cond itions apply) parameter symbol limit valu es unit test conditions / remarks min. typ. max.
TC1762 electrical parameters preliminary data sheet 79 v1.0, 2008-04 figure 4-1 adc0 clock circuit 15) i aref_max is valid for the minimum specified conversion time. the current flowing during an adc conversion with a duration of up to t c =25 s can be calculated with the formula i aref_max = q conv / t c . every conversion needs a total charge of q conv = 150pc from v aref . all adc conversions with a duration longer than t c = 25 s consume an i aref_max = 6 a. 16) for the definition of the parameters see also figure 4-2 . 17) applies to ain0 and ain1, when used as auxiliary reference inputs. 18) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smaller capacitances are successively switched to the reference voltage. 19) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before the sampling moment. because of the parasitic elements the voltage measured at ainx is lower then v aref /2. mca04657_mod programmable clock divider (1: 1) t o (1: 256) f bc f di v fract ional divider f clc f ana programmable count er sample ti me t s con. ctc chconn. stc f ti mer cont rol/ st at us logic i nt errupt logic ext ernal trigger logic ext ernal mult iplexer logic request generat ion logic a/d converter module arbit er (1: 20) control unit (timer) 1: 4
TC1762 electrical parameters preliminary data sheet 80 v1.0, 2008-04 figure 4-2 adc0 input circuits reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx
TC1762 electrical parameters preliminary data sheet 81 v1.0, 2008-04 figure 4-3 adc0 analog inputs leakage an2 to an30 v in [v ddm %] 300na 1ua 3ua 2% 95% 100% 98% ioz1 an0, an1 and an31 v in [v ddm %] 400na -1ua 3ua 2% 95% 100% 98% ioz1 300na -200na 200na 1ua -1ua -200na
TC1762 electrical parameters preliminary data sheet 82 v1.0, 2008-04 4.2.3 fast analog to digital converter (fadc) table 4-7 provides the characteristics of the fadc module in the TC1762. table 4-7 fadc characteristics (operating conditions apply) parameter symbol limit values unit remarks conditions min. max. dnl error e dnl cc ? 1 lsb 12) inl error e inl cc ? 4 lsb 12) gradient error 1)12) e grad cc ? 3 % 2) with calibration, gain 1, 2 ? 5 % without calibration gain 1, 2, 4 ? 6 % without calibration gain 8 offset error 12) e off 3) cc ? 20 4) mv 2) with calibration ?60 4) mv without calibration reference error of internal v faref /2 e ref cc ? 60 mv ? input leakage current at analog inputs an32 to an35. 5) see figure 4-5 i oz1 6) cc ?1000 300 na (0% v ddm ) < v in < (2% v ddm ) ?200 4 00 na (2% v ddm ) < v in < (95% v ddm ) ?200 1000 na (95% v ddm ) < v in < (98% v ddm ) ?200 3000 na (98% v ddm ) < v in < (100% v ddm ) analog supply voltages v ddmf sr 3.13 3.47 7) v? v ddaf sr 1.42 1.58 8) v? analog ground voltage v ssaf sr -0.1 0.1 v ? analog reference voltage v faref sr 3.13 3.47 7)9) v nominal 3.3 v analog reference ground v fagnd sr v ssaf - 0.05v v ssaf +0.05v v? analog input voltage range v ainf sr v fagnd v ddmf v?
TC1762 electrical parameters preliminary data sheet 83 v1.0, 2008-04 analog supply currents i ddmf sr ? 9 ma ? i ddaf sr ? 17 ma 10) input curren t at each v faref i faref cc ? 150 a rms independent of conversion input leakage current at v faref 11) i foz2 cc ? 500 na 0 v < v in < v ddmf input leakage current at v fagnd i foz3 cc 8 a conversion time t c cc ? 21 clk of f adc for 10-bit conv. converter clock f adc cc ? 80 mhz ? input resistance of the analog voltage path (rn, rp) r fain cc 100 200 k ? 12) channel amplifier cutoff frequency f coff cc 2 mhz ? settling time of a channel amplifier after changing enn or enp t set cc 5 sec ? 1) calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8. 2) calibration should be performed at each power-up. in case of continuous operation, calibration should be performed minimum once per week. 3) the offset error voltage drifts over the whole temperature range typically 2 lsb. 4) applies when the gain of the channel equals one. for the other gain settings, the offset error increases; it must be multiplied with the applied gain. 5) the leakage current definition is a continuous function, as shown in figure 4-5 . the numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 6) only one of these parameters is tested, the other is verified by design characterization. 7) voltage overshoot to 4 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 8) voltage overshoot to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 9) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 10) current peaks of up to 40 ma with a duration of max. 2 ns may occur table 4-7 fadc characteristics (cont?d)(operating conditions apply) parameter symbol limit values unit remarks conditions min. max.
TC1762 electrical parameters preliminary data sheet 84 v1.0, 2008-04 the calibration procedure should run afte r each power-up, wh en all power supply voltages and the reference vo ltage have stabilized. the offset calibra tion must run first, followed by the gain calibration. figure 4-4 fadc input circuits 11) this value applies in power-down mode. 12) not subject to production test, verified by design / characterization. fadc_inprefdiag = + - + - r n fainxn fainxp v fag nd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fag nd v faref i faref
TC1762 electrical parameters preliminary data sheet 85 v1.0, 2008-04 figure 4-5 analog inputs an32-an35 leakage an32 to an35 v in [v ddm %] 400na -1ua 3ua 2% 95% 100% 98% ioz1 300na -200na 1ua
TC1762 electrical parameters preliminary data sheet 86 v1.0, 2008-04 4.2.4 oscillator pins table 4-8 provides the characteristics of th e oscillator pins in the TC1762. note: it is strongly recommended to meas ure the oscillation allowance (negative resistance) in the final target system (lay out) to determine t he optimal parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. table 4-8 oscillator pins characteristics (operating conditions apply) parameter symbol limit values unit test conditions min. max. frequency range f osc cc 4 25 mhz ? input low voltage at xtal1 1) 1) if the xtal1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 v ddosc3 is necessary. v ilx sr -0.2 0.3 v ddosc3 v? input high voltage at xtal1 1) v ihx sr 0.7 v ddosc3 v ddosc3 + 0.2 v? input current at xtal1 i ix1 cc ? 25 a0 v < v in < v ddosc3
TC1762 electrical parameters preliminary data sheet 87 v1.0, 2008-04 4.2.5 temperature sensor table 4-9 provides the characteristics of th e temperature sensor in the TC1762. table 4-9 temperature sensor characteristics (operating conditions apply) parameter symbol limit values unit remarks min. max. temperature sensor range t sr sr -40 150 c ? start-up time after resets inactive t tsst sr 10 s temperature of the die at the sensor location t ts cc t ts = (adc_code - 487) 0.396 - 40 c 10-bit adc result t ts = (adc_code - 1948) 0.099 - 40 c 12bit adc result sensor inaccuracy t tsa cc 10 c a/d converter clock for dts signal f ana sr ? 10 mhz conversion with adc0
TC1762 electrical parameters preliminary data sheet 88 v1.0, 2008-04 4.2.6 power supply current table 4-10 provides the characteri stics of the power supply current in the TC1762. table 4-10 power supply current (operating conditions apply) parameter symbol limit values unit test conditions / remarks min. typ. max. porst low current at v dd i dd_porst cc ? ? 96 1) 1) maximum value measured at t a = 125 c. ma the pll running at the base frequency 138 2) 2) maximum value measured at t j = 150 c. porst low current at v ddp i ddp_porst cc ? ? 12 1) ma the pll running at the base frequency 13 2) active mode core supply current 3)4) 3) infineon power loop: cpu and pcp running, all peripherals active. the power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. 4) the i dd decreases typically to 240ma if the f cpu is decreased to 40 mhz, at constant t j = 150 c, for the infineon max. power loop. i dd cc ? ? 290 1) ma f cpu = 80mhz f cpu / f sys =1:1 330 2) active mode core supply current 3)4) i dd cc ? ? 250 1) ma f cpu = 66mhz f cpu / f sys =1:1 300 2) active mode analog supply current i ddax; i ddmx cc ? ? ? ma see adc0/fadc oscillator and pll core power supply i ddosc cc ? ? 5 ma ? oscillator and pll pads power supply i ddosc3 cc ? ? 3.6 5) 5) estimated value; double-bonded at package level with v ddp . ma ? flash power supply current i ddfl3 cc ? ? 45 ma ? lvds port supply (via v ddp ) 6) 6) in case the lvds pads are disabled, the power consumption per pair is negligible (less than 1 a). i lvds cc ? ? 25 ma lvds pads active maximum allowed power dissipation 7) 7) for the calculation of the junction to ambient thermal resistance r tja , see chapter 5.1 . p dmax sr p d r tja < 25c ? at worst case, t a =125c
TC1762 electrical parameters preliminary data sheet 89 v1.0, 2008-04 4.3 ac parameters all ac parameters are defined with the temperature compensation disabled, which means that pads are c onstantly kept at t he maximum strength. 4.3.1 testing waveforms the testing waveforms for rise /fall time, output delay an d output high impedance are shown in figure 4-6 , figure 4-7 and figure 4-8 . figure 4-6 rise/fall time parameters figure 4-7 testing waveform, output delay figure 4-8 testing waveform, output high impedance 10% 90% 10% 90% v ss v ddp t r rise_f all t f mct 04881_ll. vsd v dde / 2 te st p oin ts v dde / 2 v ss v ddp mct 04880_ll v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
TC1762 electrical parameters preliminary data sheet 90 v1.0, 2008-04 4.3.2 output rise/fall times table 4-11 provides the characteri stics of the output rise/fall times in the TC1762. table 4-11 output rise/fall times (operating conditions apply) parameter symbol limit va lues unit test conditions min. max. class a1 pads rise/fall times 1) class a1 pads 1) not all parameters are subject to production test, but verified by design/characterization and test correlation. t ra1 , t fa1 50 140 18000 150 550 65000 ns regular (medium) driver, 50 pf regular (medium) driver, 150 pf regular (medium) driver, 20 nf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a2 pads rise/fall times 1) class a2 pads t fa2 , t fa2 3.3 6 5.5 16 50 140 18000 150 550 65000 ns strong driver, sharp edge, 50 pf strong driver, sharp edge, 100pf strong driver, med. edge, 50 pf strong driver, so ft edge, 50 pf medium driver, 50 pf medium driver, 150 pf medium driver, 20 000 pf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a3 pads rise/fall times 1) class a3 pads t fa3 , t fa3 2.5 ns 50 pf class a4 pads rise/fall times 1) class a4 pads t fa4 , t fa4 2.0 ns 25 pf class c pads rise/fall times class c pads t rc, t fc 2ns
TC1762 electrical parameters preliminary data sheet 91 v1.0, 2008-04 4.3.3 power sequencing there is a restriction for the power sequ encing of the 3.3 v domain as shown in figure 4-9 . it must always be higher than 1.5 v domain - 0.5 v. the gray area shows the valid range for v 3.3v relative to an exemplary v 1.5v ramp. v ddp , v ddosc3 , v ddm , v ddmf , v ddfl3 belong to the 3. 3 v domain. the v ddm and v ddmf subdomains are connected with antiparallel esd protection di odes. there are no other su ch connections between the subdomains. v dd , v ddosc and v ddaf belong to the 1.5 v domain. figure 4-9 v ddp / v dd power up sequence all ground pins v ss must be externally c onnected to one single st ar point in the system. the difference voltage bet ween the ground pins mu st not exceed 200 mv. the porst signal must be activated at latest before any power s upply voltage falls below the levels shown on the figure below. in this case, on ly the memory row of a flash memory that was the target of the write at the moment of the power loss will contain unreliable cont ent. additionally, the porst signal should be activated as soon as possible. the sooner the porst signal is activated, the le ss time the system operates outside of the no rmal operating po wer supply range. powerseq 1.5v 3.3v v 1.5 v 3.3 v 3.3 > v 1.5 - 0.5v ti me power supply voltage v a l i d a r e a f o r v 3 . 3 v a l i d a r e a f o r v 3 . 3 time v ddp (3.3v) porst
TC1762 electrical parameters preliminary data sheet 92 v1.0, 2008-04 figure 4-10 power down / power loss sequence v ddp power supply volt age t porst v porst3.3 v ddp -5% -12% 3.3v 3.13v 2.9v v ddpmin t t porst t v dd -5% -12% 1.5v 1.42v 1.32v v dd v porst1.5min v ddmin powerdown3. 3_1. 5_reset _only_ll. vsd
TC1762 electrical parameters preliminary data sheet 93 v1.0, 2008-04 4.3.4 power, pad and reset timing table 4-12 provides the characteristics of the power, pad and reset timing in the TC1762. table 4-12 power, pad and reset timing parameters parameter symbol limit values unit min. max. min. v ddp voltage to en sure defined pad states 1) 1) this parameter is valid under assumption that porst signal is constantly at low-level during the power- up/power-down of the v ddp . v ddppa cc 0.6 ? v oscillator start-up time 2) t oscs cc ? 10 ms minimum porst active time after power supplies are st able at operating levels t poa sr 10 ? ms hdrst pulse width t hd cc 1024 clock cycles 3) ? f sys porst rise time t por sr ? 50 ms setup time to porst rising edge 4) t pos sr 0 ? ns hold time from porst rising edge 4) t poh sr 100 ? ns setup time to hdrst rising edge 5) t hds sr 0 ? ns hold time from hdrst rising edge 5) t hdh sr 100 + (2 1/ f sys ) ?ns ports inactive after porst reset active 6)7) t pip cc ? 150 ns ports inactive after hdrst reset active 8) t pi cc ? 150 + 5 1/ f sys ns minimum v ddp porst activation threshold. 9) v porst3.3 sr ? 2.9 v minimum v dd porst activation threshold. 9) v porst1.5 sr ? 1.32 v power-on reset boot time 10) t bp cc 2.15 3.50 ms hardware/software reset boot time at f cpu =80mhz 11) t b cc 500 800 s hardware/software reset boot time at f cpu =66mhz 11) t b cc 560 860 s
TC1762 electrical parameters preliminary data sheet 94 v1.0, 2008-04 figure 4-11 power, pad and reset timing 2) this parameter is verified by device characterization. the external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) any hdrst activation is internally prolonged to 1024 fpi bus clock ( f sys ) cycles. 4) applicable for input pins testmode , trst , brkin , and txd1a with noise suppression filter of porst switched-on (bypass = 0). 5) the setup/hold values are applicable for port 0 and port 4 input pins with noise suppression filter of hdrst switched-on (bypass = 0), independently whether hdrst is used as input or output. 6) not subject to production test, verified by design / characterization. 7) this parameter includes the delay of the analog spike filter in the porst pad. 8) not subject to production test, verified by design / characterization. 9) in case of power loss during internal flash write, prevents flash write to random address. 10) booting from flash, the duration of the boot-time is defined between the rising edge of the porst and the moment when the first user instruction has entered the cpu and its processing starts. 11) booting from flash, the duration of the boot time is defined between the following events: 1. hardware reset: the falling edge of a short hdrst pulse and the moment when the first user instruction has entered the cpu and its processing starts, if the hdrst pulse is shorter than 1024 t sys . if the hdrst pulse is longer than 1024 t sys , only the time beyond the 1024 t sys should be added to the boot time (hdrst falling edge to first user instruction). 2. software reset: the moment of starting the software reset and the moment when the first user instruction has entered the cpu and its processing starts reset_beh 1) as programmed vddp porst hdrst pads pad- state undefined t pi vdd v ddppa v ddppa pad- state undefined 2) tri-state, pull device active t hd v ddpr osc t oscs 1) 2) 1) 2) 2) t poa t poa t hd
TC1762 electrical parameters preliminary data sheet 95 v1.0, 2008-04 4.3.5 phase locked loop (pll) section 4.3.5 provides the characteristics of the p ll parameters and its operation in the TC1762. note: all pll characteristics de fined on this and t he next page are ve rified by design characterization. phase locked loop operation when pll operation is enabled and configur ed, the pll clock f vco (and with it the cpu clock f cpu ) is constantly adjusted to the sele cted frequency. the relation between f vco and f sys is defined by: f vco =k f cpu . the pll causes a jitter of f cpu and affects the clock outputs trclk and sy sclk (p4.3) which are de rived from the pll clock f vco . there are two formulas that de fine the (absolute) approxim ate maximum value of jitter d p in ns dependent on the k-factor, the cpu clock frequency f cpu in mhz, and the number p of consecutive f cpu clock periods. (4.1) (4.2) k : k-divider value p : number of f cpu periods d p : jitter in ns f cpu : cpu frequency in mhz table 4-13 pll parameters (operating conditions apply) parameter symbol limit values unit min. max. accumulated jitter d p see figure 4-12 ? vco frequency range f vco 400 500 mhz 500 600 mhz 600 700 mhz pll base frequency 1) 1) the cpu base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the k factor after reset). f pllbase 140 320 mhz 150 400 mhz 200 480 mhz pll lock-in time t l ? 200 s p k 900 < dp ns [] 5p fcpu mhz [] ----------------------------- 0 9 , + ?? ?? = p k 900 dp ns [] 4500 fcpu mhz [] k ---------------------------------------- 0 9 , + ?? ?? =
TC1762 electrical parameters preliminary data sheet 96 v1.0, 2008-04 note: the frequency of system clock f sys can be selected to be either f cpu or f cpu /2. with rising number p of clock cycles the ma ximum jitter increases linearly up to a value of p that is defined by the k-factor of the pll. beyond this value of p the maximum accumulated jitter remains at a constant value. further, a lower cpu clock frequency f cpu results in a higher abso lute maximum jitter value. figure 4-12 illustrates the jitter cu rve for for several k/ f cpu combinations. figure 4-12 approximated maximum accumulated pll jitter for typical cpu clock frequencies f cpu (overview) 1 0 .0 p [p eriods] 1 .0 2 .0 3.0 5.0 25 50 75 100 125 150 4.0 175 TC1762 pll jitter ( pr eliminar y) 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 jitter [ns] f cpu = 80 mhz ( k = 8) f cpu = 80 mhz ( k = 5) f cpu = 66 mhz ( k = 7) f cpu = 66 mhz ( k = 10) f cpu = 40 mhz f cpu = 40 mhz ( k = 10) ( k = 17) oo
TC1762 electrical parameters preliminary data sheet 97 v1.0, 2008-04 figure 4-13 approximated maximum accumulated pll jitter for typical cpu clock frequencies f cpu (detail) note: the maximum peak-to-p eak noise on the main osc illator and pll power supply (measured between v ddosc and v ssosc ) is limited to a peak -to-peak voltage of v pp = 10 mv. this condition can be achiev ed by appropriate blo cking to the supply pins and using pcb supp ly and ground planes. 1 0 .9 0 1 .0 0 1 .1 0 1.40 23 45 TC1762 pll jitter (preliminary ) 1.20 1.30 jitter [ ns] p [periods] f cpu = 40 mhz f cpu = 66 mhz f cpu = 80 mhz
TC1762 electrical parameters preliminary data sheet 98 v1.0, 2008-04 4.3.6 debug trace timing v ss = 0 v; v ddp = 3.13 to 3.47 v (class a); t a = -40 c to +125 c; c l (trclk) = 25 pf; c l (tr[15:0]) = 50 pf figure 4-14 debug trace timing table 4-14 debug trace timing parameter 1) 1) not subject to production test, verified by design/characterization. parameter symbol limit values unit min. max. tr[15:0] new st ate from trclk t 9 cc -1 4 ns trace_tmg trclk t 9 tr[15:0] old state new state
TC1762 electrical parameters preliminary data sheet 99 v1.0, 2008-04 4.3.7 timing for jtag signals (operating conditions apply, c l = 50 pf) figure 4-15 tck clock timing table 4-15 tck clock timing parameter parameter symbol limit values unit min. max. tck clock period 1) 1) f tck should be lower or equal to f sys t tck sr 25 ? ns tck high time t 1 sr 10 ? ns tck low time t 2 sr 10 ? ns tck clock rise time t 3 sr ? 4 ns tck clock fall time t 4 sr ? 4 ns tck t 4 0.9 v dd t 3 t 1 0.1 v dd t 2 t tck 0.5 v dd
TC1762 electrical parameters preliminary data sheet 100 v1.0, 2008-04 table 4-16 jtag timing parameter 1) 1) not subject to production test, verified by design / characterization. parameter symbol limit values unit test conditions / remarks min. max. tms setup to tck t 1 sr 6.0 ? ns ? tms hold to tck t 2 sr 6.0 ? ns ? tdi setup to tck t 1 sr 6.0 ? ns ? tdi hold to tck t 2 sr 6.0 ? ns ? tdo valid output from tck 2) 2) the falling edge on tck is used to capture the tdo timing. t 3 cc ? 14.5 ns c l = 50 pf 3)4) 3) by reducing the load from 50 pf to 20 pf, a reduction of approximately 1.0 ns in timing is expected. 4) by reducing the power supply range from +/-5 % to +5/-2 %, a reduction of approximately 0.5 ns in timing is expected. 3.0 ? c l = 20 pf tdo high impedanc e to valid output from tck 2) t 4 cc ? 15.5 ns c l = 50 pf 3)4) tdo valid output to high impedance from tck 2) t 5 cc ? 14.5 ns c l = 50 pf 4)
TC1762 electrical parameters preliminary data sheet 101 v1.0, 2008-04 figure 4-16 jtag timing note: the jtag module is fully compliant with ieee1149.1-200 0 with jtag clock at 20 mhz. the jtag clock at 40 mhz is po ssible with the modified timing diagram shown in figure 4-16 . tms tdi tck tdo t 1 t 2 t 1 t 2 t 4 t 3 t 5
TC1762 electrical parameters preliminary data sheet 102 v1.0, 2008-04 4.3.8 peripheral timings section 4.3.8 provides the characteristics of the peripheral timings in the TC1762. note: peripheral timing parameters are not su bject to production test. they are verified by design/characterization. 4.3.8.1 micro link interface (mli) timing table 4-17 provides the characteristics of the mli timing in the TC1762. table 4-17 mli timing (operating conditions apply, c l = 50 pf) parameter symbol limit values unit min. max. tclk clock period 1)2) 1) tclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) tclk high and low times can be minimum 1 t mli t 30 cc 2 3) 3) t mlimin = t sys = 1/ f sys . when f sys = 80mhz, t 30 = 25ns ?1/ f sys rclk clock period t 31 sr 1 ? 1/ f sys mli outputs delay from tclk t 35 cc 0 8 ns mli inputs setup to rclk t 36 sr 4 ? ns mli inputs hold to rclk t 37 sr 4 ? ns rready output delay from rclk t 38 cc 0 8 ns
TC1762 electrical parameters preliminary data sheet 103 v1.0, 2008-04 figure 4-17 mli interface timing note: the generation of rreadyx is in t he input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. mli_tmg_1.vsd tdatax tvalidx t 35 t 35 t 37 t 36 tclkx 0.1 v ddp 0.9 v ddp rdatax rvalidx rclkx t 30 treadyx rreadyx t 38 t 38 t 30
TC1762 electrical parameters preliminary data sheet 104 v1.0, 2008-04 4.3.8.2 micro second channel (msc) interface timing table 4-18 provides the charac teristics of the msc timing in the TC1762. figure 4-18 msc interface timing note: the data at sop should be sampled with the falling edge of fclp in the target device. table 4-18 msc interface timing (operating conditions apply, cl = 50 pf) parameter symbol limit values unit min. max. fclp clock period 1)2) 1) fclp signal rise/fall times are the same as the a2 pads rise/fall times. 2) fclp signal high and low can be minimum 1 t msc . t 40 cc 2 t msc 3) 3) t mscmin = t sys = 1/ f sys . when f sys = 80mhz, t 40 = 25ns ?ns sop/enx outputs delay from fclp t 45 cc -10 10 ns sdi bit time t 46 sr 8 t msc ?ns sdi rise time t 48 sr 100 ns sdi fall time t 49 sr 100 ns msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi
TC1762 electrical parameters preliminary data sheet 105 v1.0, 2008-04 4.3.8.3 synchronous serial channel (ssc) master mode timing table 4-19 provides the characteristics of the ssc timi ng in the TC1762. figure 4-19 ssc master mode timing table 4-19 ssc master mode timing (operating conditions a pply, cl = 50 pf) parameter symbol limit values unit min. max. sclk clock period 1)2) 1) sclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) sclk signal high and low times can be minimum 1 t ssc . t 50 cc 2 t ssc 3) 3) t sscmin = t sys = 1/ f sys . when f sys = 80 mhz, t 50 = 25ns ?ns mtsr/slsox delay from sclk t 51 cc 0 8 ns mrst setup to sclk t 52 sr 10 ? ns mrst hold from sclk t 53 sr 5 ? ns ssc_tmg_1.vsd sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slsox 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slsox is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50
TC1762 packaging preliminary data sheet 106 v1.0, 2008-04 5 packaging chapter 5 provides the information of the tc 1762 package and reliability section. 5.1 package parameters table 5-1 provides the characteristi cs of the pack age parameters. table 5-1 package parameters (pg-lqfp-176-2) parameter symbol limit values unit notes min. max. thermal resistance junction case top 1) 1) the thermal resistances between the case top and the ambient (r tcat ), the leads and the ambient (r tla ) are to be combined with the thermal resistances between the junction and the case top (r tjct ), the junction and the leads (r tjl ) given above, in order to calculate the total thermal resistance between the junction and the ambient (r tja ). the thermal resistances between the case top and the ambient (r tcat ), the leads and the ambient (r tla ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j =t a +r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances. r tjct cc ? 5.4 k/w ? thermal resistance junction leads 1) r tjl cc ? 21.5 k/w ?
TC1762 packaging preliminary data sheet 107 v1.0, 2008-04 5.2 package outline figure 5-1 shows the package outl ines of the TC1762. figure 5-1 package outl ines pg-lqfp-176-2 pg-lqfp-176-2 plastic low profile quad flat package y ou can find all of our packages, so rts of packing and others in our infineon internet page ?products? : http://www.infineon.com/products. dimensions in mm smd = surface mounted device
TC1762 packaging preliminary data sheet 108 v1.0, 2008-04 5.3 flash memory parameters the data retention ti me of the TC1762?s flash memory (i .e. the time after which stored data can still be retrieved) depends on the number of times the fl ash memory has been erased and programmed. table 5-2 flash parameters parameter symbol limit values unit notes min. max. program flash retention time, physical sector 1) 2) 1) storage and inactive time included. 2) at average weighted junction temperature t j = 100 c, or the retention time at average weighted temperature of t j = 110 c is minimum 10 years, or the retention time at average weighted temperature of t j = 150 c is minimum 0.7 years. t ret 20 ? years max. 1000 erase/program cycles program flash retention time, logical sector 1)2) t retl 20 ? years max. 50 erase/program cycles data flash endurance (32 kbyte) n e 15 000 ? ? max. data retention time 5 years data flash endurance, eeprom emulation (8 4 kbyte) n e8 120 000 ? ? max. data retention time 5 years programming time per page 3) 3) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5ms. t pr ?5ms? program flash erase time per 256-kbyte sector t erp ?5s f cpu =80 mhz data flash erase time per 16-kbyte sector t erd ?0.625s f cpu =80 mhz wake-up time t wu 4300 1/ f cpu +40 s
TC1762 packaging preliminary data sheet 109 v1.0, 2008-04 5.4 quality declaration table 5-3 shows the characteristics of t he quality parameters in the TC1762. note: information about sold ering can be found on the ?package? information page under: http://www.infineon.com/products . table 5-3 quality parameters parameter symbol limit values unit notes min. max. operation lifetime 1)2) 1) this lifetime refers only to the time when the device is powered-on. 2) an example of a detailed tem perature profile is as below: 2000 hours at t j = 150 o c 16000 hours at t j = 125 o c 6000 hours at t j = 110 o c this example is equivalent to the operation lifetime and average temperatures given in table 5-3 . t op ? 24000 hours at average weighted junction temperature t j = 127c ? 66000 hours at average weighted junction temperature t j = 100c ? 20 years at average weighted junction temperature t j = 85c esd susceptibility according to human body model (hbm) v hbm ? 2000 v conforming to eia/jesd22- a114-b esd susceptibility of the lvds pins v hbm1 ?500v? esd susceptibility according to charged device model (cdm) pins v cdm ? 500 v conforming to jesd22-c101-c moisture sensitivity level (msl) - ? 3 v conforming to j-std-020c for 240c
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